The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Chandra Gurram, Folsom, CA (US);

Wei-Yu Chen, San Jose, CA (US);

Vikranth Vemulapalli, Folsom, CA (US);

Subramaniam Maiyuran, Gold River, CA (US);

Jorge Eduardo Parra Osorio, El Dorado Hills, CA (US);

Shuai Mu, San Diego, CA (US);

Guei-Yuan Lueh, San Jose, CA (US);

Supratim Pal, Folsom, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5016 (2013.01); G06F 9/3851 (2013.01); G06F 9/3888 (2023.08); G06F 9/4843 (2013.01); G06T 1/20 (2013.01);
Abstract

Provision of multiple register allocation sizes for threads is described. An example of a system includes one or more processors including a graphics processor, the graphics processor including at least a first local thread dispatcher (TDL) and multiple processing resources, each processing resource including a plurality of registers; and memory for storage of data for processing, wherein the one or more processors are to determine a register size for a first thread; identify one or more processing resources having sufficient register space for the first thread; select a processing resource of the one or more processing resources having sufficient register space to assign the first thread; select an available thread slot of the selected processing resource for the first thread; and allocate registers of the selected processing resource for the first thread.


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