This inventor holds 4 USPTO granted patents. Top assignee: Mentor Graphics Corporation. Active years: 2013-2020.
Location History:
- Grenoble, FR (2013)
- Portland, OR (US) (2020)
Company Filing History:
Years Active: 2013-2020
Title: Innovations of Vasileios Kourkoulos
Introduction
Vasileios Kourkoulos is an accomplished inventor based in Portland, OR (US). He has made significant contributions to the field of integrated circuit design, holding a total of 4 patents. His work focuses on enhancing the efficiency and accuracy of electrical parasitic extraction in circuit layouts.
Latest Patents
Kourkoulos's latest patents include innovative techniques for computing electric coupling in integrated circuits. One of his notable patents, titled "Through silicon vias to interconnect electrical parasitic extraction," discloses tools and techniques for calculating parasitic admittance and capacitance values between through silicon vias (TSVs) and surrounding interconnects. This invention utilizes multiple field solvers to establish electrical connectivity and generate a parasitic netlist representation of the circuit layout.
Another significant patent is "Machine learning-based parasitic extraction automation for circuit design and verification." This application describes a computing system that implements a parasitic extraction tool to generate netlists from test cases. The system iteratively adjusts scaling coefficients to minimize differences between generated parasitic netlists and reference netlists, ensuring high accuracy in circuit design.
Career Highlights
Kourkoulos is currently employed at Mentor Graphics Corporation, where he continues to innovate in the field of circuit design. His expertise in parasitic extraction has positioned him as a valuable asset to the company and the industry.
Collaborations
He has collaborated with notable colleagues, including Roberto Suaya and Georgios Manetas, contributing to various projects that enhance the capabilities of integrated circuit design.
Conclusion
Vasileios Kourkoulos is a prominent inventor whose work in electrical parasitic extraction has advanced the field of integrated circuit design. His innovative patents and contributions to Mentor Graphics Corporation highlight his commitment to improving circuit efficiency and accuracy.