Mentor Graphics Corporation

Vasileios Kourkoulos

Roberto Suaya

Rengjing Zhang

Georgios Manetas

Joshua Adkins

Disclosed herein are embodiments of tools and techniques for computing the electric coupling in terms of parasitic admittance and capacitance values between a through silicon via (TSV) and surrounding interconnect of an integrated circuit layout design. In particular embodiments, a computation of one or more admittance and capacitance values between a through-silicon-via (TSV) structure and an interconnect structure of the three-dimensional integrated circuit layout design using two or more field solvers or rule-based engines that are different from one another is performed. In addition, electrical connectivity for the coupling parasitic between a TSV and an interconnect is established. Then, a parasitic netlist representation of the three-dimensional integrated circuit layout design that includes the above parasitic element values is generated.

Through silicon vias to interconnect electrical parasitic extraction

This application discloses a computing system implementing a parasitic extraction tool to generate parasitic netlists from tests cases including test layout models of integrated circuit structures. The test cases include reference netlists corresponding to intended parasitic netlists for the test layout models. The computing system can determine values for scaling coefficients that, when utilized by the parasitic extraction tool to generate the parasitic netlists, allow differences between the parasitic netlists and the reference netlists to fall below threshold levels. The determination of the scaling coefficients is performed by iteratively adjusting the values of the scaling coefficients based on differences between the reference netlists and the parasitic netlists generated with the scaling coefficients having the adjusted values. The computing system can utilize the adjusted scaling coefficients to generate parasitic netlists having differences with the reference netlists that fall below threshold levels of the test cases.

Machine learning-based parasitic extraction automation for circuit design and verification

Aspects of the invention relate to techniques for extracting admittance values associated with through-silicon vias in an integrated circuit system. A function fitting process is performed to generate parameters of a representation for electro-quasi-static potential Green's functions at a plurality of frequencies of interest based on integrated circuit manufacturing process information. Based on the generated parameters, a set of electric potential basis functions, a set of electric displacement basis functions and layout information for a layout design of interest, matrix elements of a matrix for each frequency in the plurality of frequencies of interest may be computed. The matrix is a part of a linear system that formulates a relationship of electric displacement fields and electric potentials in various regions associated with through-silicon vias in the layout design. Based on the matrix, admittance values associated with the through-silicon vias are computed.

Through-silicon via admittance extraction

Aspects of the invention relate to techniques for extracting impedance values associated with through-silicon vias in an integrated circuit system. A function fitting process is performed to generate parameters of a representation for magneto-quasi-static dyadic vector potential Green's functions at a plurality of frequencies of interest based on integrated circuit manufacturing process information. Based on the generated parameters, a set of electric current basis functions and the layout information for a layout design of interest, matrix elements of a matrix for each frequency in the plurality of frequencies of interest may be computed. The matrix is a part of a linear system that formulates a relationship of electric current and electric potential difference in various regions associated with the through-silicon vias in the layout design. Based on the matrix, impedance values associated with the through-silicon vias are computed.

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Portland, OR, United States of America

Vasileios Kourkoulos