The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
Sep. 29, 2018
Mentor Graphics Corporation, Wilsonville, OR (US);
Vasileios Kourkoulos, Portland, OR (US);
Georgios Manetas, Grenoble, FR;
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
Disclosed herein are embodiments of tools and techniques for computing the electric coupling in terms of parasitic admittance and capacitance values between a through silicon via (TSV) and surrounding interconnect of an integrated circuit layout design. In particular embodiments, a computation of one or more admittance and capacitance values between a through-silicon-via (TSV) structure and an interconnect structure of the three-dimensional integrated circuit layout design using two or more field solvers or rule-based engines that are different from one another is performed. In addition, electrical connectivity for the coupling parasitic between a TSV and an interconnect is established. Then, a parasitic netlist representation of the three-dimensional integrated circuit layout design that includes the above parasitic element values is generated.