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For the Inventor, By the Inventor

Salem, India

Umamaheshwaran V

This inventor holds 9 USPTO granted patents and 1 published patent application. Top assignee: Qualcomm Incorporated. Active years: 2025-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Umamaheshwaran V. Retrieved from https://idiyas.com/inventor/umamaheshwaran-v

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 9 

% Patents Active = 66.7

Average Co-Inventor Count = 4.1

ph-index = 1


Company Filing History:

goldMedal9 out of 44,897 
 
Qualcomm Incorporated
 patents

Years Active: 2025-2026

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9 patents (USPTO):Explore Patents
1. 12724679 - Systems and methods for avoiding retraining a communication bus after a link failure (2026-09-01),
2. 12608289 - Interconnect link with a resilient link mode based on a link status register (2026-04-21),
3. 12579017 - Apparatus and methods for securing integrity and data encryption link sessions within die interconnect architectures (2026-03-17),
4. 12499077 - Variable link width in two directions for main band chip module connection (2025-12-16),
5. 12430280 - Mechanism to improve the reliability of sideband in chiplets (2025-09-30),
6. 12399853 - Mechanism to improve link initialization time (2025-08-26),
7. 12386382 - Reduced training for main band chip module interconnection clock lines (2025-08-12),
8. 12380047 - Expanded data link width for main band chip module connection in alternate modes (2025-08-05),
9. 12314204 - Single clock lane operation for a main band of a die-to-die connection (2025-05-27),

Title: Innovations by Umamaheshwaran V: Pioneering Advances in Chiplet Technology

Introduction

Umamaheshwaran V is a notable inventor based in Salem, Indiana, recognized for his contributions to the field of chiplet technology. With a total of five patents to his name, he has made significant strides in improving the reliability and efficiency of interconnections in computing devices. His work is primarily associated with Qualcomm Incorporated, where he continues to innovate and develop cutting-edge solutions.

Latest Patents

Umamaheshwaran V's latest patents include a "Mechanism to improve the reliability of sideband in chiplets." This invention encompasses various methods and devices for implementing Universal Chiplet Interconnect Express (UCIe) link configuration for multi-module chiplets. The embodiments of this patent detail the process of transitioning a UCIe link from an active state to a reset state while initializing different functional sidebands. Additionally, he has developed a "Mechanism to improve link initialization time," which involves managing interconnections between chiplets through sideband link training. This method enhances the efficiency of link state communication by designating functional pairs for data transmission.

Career Highlights

Throughout his career, Umamaheshwaran V has demonstrated a commitment to advancing technology in the semiconductor industry. His innovative approaches have not only contributed to Qualcomm's success but have also set new standards in chiplet interconnectivity. His expertise in this area has made him a valuable asset to his team and the broader tech community.

Collaborations

Umamaheshwaran has collaborated with talented individuals such as Ravindranath Doddi and Lekhya Pavani Godavarthi. These collaborations have fostered a creative environment that encourages the exchange of ideas and the development of groundbreaking technologies.

Conclusion

Umamaheshwaran V's work exemplifies the spirit of innovation in the tech industry, particularly in the realm of chiplet technology. His patents reflect a deep understanding of the complexities involved in interconnectivity, paving the way for future advancements. His contributions are a testament to the impact of dedicated inventors in shaping the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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