The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Apr. 13, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Ravindranath Doddi, Hyderabad, IN;

Lekhya Pavani Godavarthi, Hyderabad, IN;

Umamaheshwaran V, Salem, IN;

Afreen Haider, Muzaffarpur, IN;

Harinatha Reddy Ramireddy, Hyderabad, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G06F 11/07 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/405 (2013.01); G06F 11/0772 (2013.01); G06F 13/4295 (2013.01); G06F 1/04 (2013.01);
Abstract

Aspects relate to single clock lane operation for a main band of a die-to-die connection. In one aspect, a single clock mode is enabled. A method includes sending a switch to single clock mode request from a module of a first die to a module partner of a second die through a sideband to request to enable a single clock mode of a main band of a die-to-die connection that connects the first die module to the second die module partner. A switch to single clock mode response is received from the module partner through the sideband to enable the single clock mode and data is communicated with the module partner through the main band in the single clock mode using a functional clock.


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