logo

For the Inventor, By the Inventor

San Jose, CA, United States of America

Tzung-Chin Chang

USPTO Granted Patents = 28

Average Co-Inventor Count = 7.3

ph-index = 10

Forward Citations = 386(Granted Patents)


Company Filing History:

goldMedal28 out of 4,285 
 
Altera Corporation
 patents

Years Active: 2003-2010

Loading Chart...
28 patents (USPTO):Explore Patents
1. 7725755 - Self-compensating delay chain for multiple-date-rate interfaces (2010-05-25),
2. 7710149 - Input buffer for multiple differential I/O standards (2010-05-04),
3. 7425844 - Input buffer for multiple differential I/O standards (2008-09-16),
4. 7308659 - Apparatus and method for RTL modeling of a register (2007-12-11),
5. 7295040 - High speed IO buffer using auxiliary power supply (2007-11-13),
6. 7221193 - On-chip termination with calibrated driver strength (2007-05-22),
7. 7218155 - Techniques for controlling on-chip termination resistance using voltage range detection (2007-05-15),
8. 7215143 - Input buffer for multiple differential I/O standards (2007-05-08),
9. 7212054 - DLL with adjustable phase shift using processed control signal (2007-05-01),
10. 7205806 - Loop circuitry with low-pass noise filter (2007-04-17),
11. 7200769 - Self-compensating delay chain for multiple-date-rate interfaces (2007-04-03),
12. 7119579 - Supply voltage detection circuit (2006-10-10),
13. 7098690 - Programmable I/O element circuit for high speed logic devices (2006-08-29),
14. 7091760 - DLL with adjustable phase shift using processed control signal (2006-08-15),
15. 7088140 - High speed IO buffer using auxiliary power supply (2006-08-08),

Title: Innovations and Patents of Tzung-Chin Chang

Introduction

Tzung-Chin Chang, located in San Jose, California, is an accomplished inventor with an impressive portfolio of 28 patents. His work showcases innovative solutions in the field of integrated circuits and electronic systems, contributing significantly to advancements in technology.

Latest Patents

Among his most recent patents is the "Self-compensating delay chain for multiple-date-rate interfaces," which outlines methods and apparatus for delaying a clock signal in a multiple-data-rate interface. This integrated circuit comprises a frequency divider that processes a first clock signal, coupled with a variable-delay block to adjust the timing precisely. The design also includes a phase detector and an up/down counter for enhanced accuracy in clock signal management.

Another significant patent is the "Input buffer for multiple differential I/O standards." This invention features an input buffer circuit with several selectively enabled differential amplifier circuits designed for compatibility with different differential I/O standards. It allows the circuit to adapt its operations based on the required differential input signals, showcasing versatility in handling various input ranges.

Career Highlights

Tzung-Chin Chang has spent a prominent part of his career at Altera Corporation, where he has been instrumental in designing and inventing cutting-edge technologies that enhance data processing and communication within electronic systems. His contributions have propelled Altera’s reputation as a leader in the semiconductor industry.

Collaborations

Throughout his tenure, Tzung-Chin collaborated with talented colleagues such as Chiakang Sung and Khai Nguyen. These partnerships have led to the development of innovative solutions and patents that demonstrate the power of teamwork in driving technological progress.

Conclusion

Tzung-Chin Chang's impressive body of work and extensive patent portfolio reflect his commitment to innovation in the tech industry. As he continues to push the boundaries of integrated circuit design and differential I/O systems, he remains a vital figure in advancing modern technology.

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…