The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7221193 B1

PDF
Full Text
Expired
Date of Patent:
May. 22, 2007

Filed:

Jan. 20, 2005
Applicants:

Xiaobao Wang, Cupertino, CA (US);

Tzung-chin Chang, San Jose, CA (US);

Chiakang Sung, Milipitas, CA (US);

Khai Q. Nguyen, San Jose, CA (US);

Inventors:

Xiaobao Wang, Cupertino, CA (US);

Tzung-Chin Chang, San Jose, CA (US);

Chiakang Sung, Milipitas, CA (US);

Khai Q. Nguyen, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using calibration circuits. Each calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When the effective resistance of the group of transistors matches the external resistance, the calibration circuit causes the effective resistance of drive transistors in the IO buffer to match the effective resistance of the group of on-chip transistors.


Find Patent Forward Citations

Wang, Xiaobao. (2007). On-chip termination with calibrated driver strength (U.S. Patent No. 7221193). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7221193

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