The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 2007
Filed:
Jan. 02, 2002
Yan Chong, Mountain View, CA (US);
Chiakang Sung, Milpitas, CA (US);
Bonnie I. Wang, Cupertino, CA (US);
Joseph Huang, San Jose, CA (US);
Xiaobao Wang, Santa Clara, CA (US);
Philip Pan, Fremont, CA (US);
Tzung-chin Chang, San Jose, CA (US);
Yan Chong, Mountain View, CA (US);
Chiakang Sung, Milpitas, CA (US);
Bonnie I. Wang, Cupertino, CA (US);
Joseph Huang, San Jose, CA (US);
Xiaobao Wang, Santa Clara, CA (US);
Philip Pan, Fremont, CA (US);
Tzung-Chin Chang, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.