The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2007
Filed:
Jan. 20, 2005
Tzung-chin Chang, San Jose, CA (US);
Xiaobao Wang, Cupertino, CA (US);
Henry Kim, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Khai Q. Nguyen, San Jose, CA (US);
Bonnie Wang, Cupertino, CA (US);
Jeffrey Tyhach, Sunnyvale, CA (US);
Gopinath Rangan, San Francisco, CA (US);
Tzung-Chin Chang, San Jose, CA (US);
Xiaobao Wang, Cupertino, CA (US);
Henry Kim, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Khai Q. Nguyen, San Jose, CA (US);
Bonnie Wang, Cupertino, CA (US);
Jeffrey Tyhach, Sunnyvale, CA (US);
Gopinath Rangan, San Francisco, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.