EPO Patents = 4 (Patent Applications = 1)

Average Co-Inventor Count = 3.2

ph-index = 19

Forward Citations = 1,024(Granted Patents)

Location History:

Milpitas, CA (US) (1998 - 2007)
Cupertino, CA (US) (2010 - 2013)

Company Filing History:

Institute for the Development of Emerging Architectures, L.l.c.

Years Active: 1998-2013

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42 patents (USPTO):Sort by Forward Citations

Abstract keywords

1. 8566528 - Combining write buffer with dynamically adjustable flush metrics (2013-10-22),

2. 8352685 - Combining write buffer with dynamically adjustable flush metrics (2013-01-08),

3. 8255670 - Replay reduction for power saving (2012-08-28),

4. 8171326 - L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down (2012-05-01),

5. 8171240 - Misalignment predictor (2012-05-01),

6. 8117404 - Misalignment predictor (2012-02-14),

7. 7996646 - Efficient encoding for detecting load dependency on store with misalignment (2011-08-09),

8. 7752474 - L1 cache flush when processor is entering low power mode (2010-07-06),

9. 7721066 - Efficient encoding for detecting load dependency on store with misalignment (2010-05-18),

10. 7647518 - Replay reduction for power saving (2010-01-12),

11. 7269714 - Inhibiting of a co-issuing instruction in a processor having different pipeline lengths (2007-09-11),

12. 7203817 - Power consumption reduction in a pipeline by stalling instruction issue on a load miss (2007-04-10),

13. 7162613 - Mechanism for processing speculative LL and SC instructions in a pipelined processor (2007-01-09),

14. 7100064 - Limiting performance in an integrated circuit to meet export restrictions (2006-08-29),

15. 6976152 - Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard (2005-12-13),

Title: The Innovative Contributions of Tse-Yu Yeh

Introduction

Tse-Yu Yeh, based in Cupertino, CA, has made significant contributions to the field of technology and innovation. With an impressive portfolio of 42 patents, he stands out as a prominent inventor, pushing the boundaries of what is possible in modern computing and memory management.

Latest Patents

Among Tse-Yu Yeh's most recent work is a patent titled "Combining Write Buffer with Dynamically Adjustable Flush Metrics." This innovation focuses on a combining write buffer designed to maintain various flush metrics to determine the optimal timing for transmitting write operations from buffer entries. Significantly, this technology allows for the dynamic modification of these flush metrics based on ongoing activity within the write buffer. Notably, one implementation categorizes write buffer entries as 'collapsed,' where a collapsed entry may comprise write operations that have overwritten previous data. Additionally, this combining write buffer adjusts the threshold of buffer fullness as a flush metric, which enhances system performance over time.

Career Highlights

Tse-Yu Yeh's career spans significant experience at leading technology companies, including Intel Corporation and Apple Inc. His work in these organizations has contributed to numerous advancements in memory management technologies, influencing the computing landscape.

Collaborations

Throughout his career, Tse-Yu Yeh has collaborated with notable professionals, including Mircea Poplingher and Po-Yung Chang. These partnerships have likely enriched his projects, combining diverse perspectives and expertise in the pursuit of innovative solutions.

Conclusion

Tse-Yu Yeh exemplifies the spirit of innovation, with a dedicated focus on improving memory management through advanced technologies. His contributions, particularly in the realm of write buffer mechanisms, continue to shape the future of computing systems, ensuring enhanced performance and efficiency. As he progresses in his career, the tech industry can look forward to more groundbreaking inventions from this remarkable inventor.

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4 patents (EPO):

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1 patent pending (EPO):

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