The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2007
Filed:
Jan. 28, 2005
Tse-yu Yeh, Milpitas, CA (US);
Po-yung Chang, Saratoga, CA (US);
Mark H. Pearce, San Francisco, CA (US);
Zongjian Chen, Palo Alto, CA (US);
Tse-Yu Yeh, Milpitas, CA (US);
Po-Yung Chang, Saratoga, CA (US);
Mark H. Pearce, San Francisco, CA (US);
Zongjian Chen, Palo Alto, CA (US);
Broadcom Corporation, Irvine, CA (US);
Abstract
A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.