Intel Corporation

Apple Inc.

Broadcom Corporation

Institute for the Development of Emerging Architectures, L.l.c.

Idea Corporation

Tse-Yu Yeh

Mircea Poplingher

Po-Yung Chang

Ramesh B Gunna

Michael Paul Corwin

Wenliang Chen

James B Keller

Dale Calvin Morris

Harshvardhan P Sharangpani

Wei-Han Lien

Hans J Mulder

Robert Rogenmoser

Kent G Fielden

Carl C Scafidi

Mitchell Alexander Poplingher

Monis Rahman

Sujat Jamil

Michael S Schlansker

Rajiv Gupta

Nazar A Zaidi

Brian J Campbell

Brian P Lilly

Achmed Rumi Zahir

Ralph Michael Kling

Daniel C Murray

Zongjian Chen

Peter J Bannon

Andrew J Beaumont-Smith

Shih-Chieh Wen

David A Kruckemyer

Judge K Arora

Mark Pearce

Eric Hao

Anup S Mehta

Vincent E Hummel

Jesse Pan

Jaidev Prasad Patwardhan

Eric Sindelar

Rory McInerney

Millind Mittal

Gary N Hammond

Steven J Tu

Sailesh Kottapalli

Ashish V Choubal

Gregory Scott Mathews

Robert Stepanian

Kin-Yip Liu

Keshavram N Murty

Kalpana Ramakrishnan

Michael C Kim

Randel P Blake-Campos

Jignesh Trivedi

James Hull

Darshana S Shah

PoYung Chang

Mark H Pearce

In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as 'collapsed.' A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

Combining write buffer with dynamically adjustable flush metrics

In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.

Replay reduction for power saving

In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.

L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down

In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.

Misalignment predictor

In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.

Efficient encoding for detecting load dependency on store with misalignment

L1 cache flush when processor is entering low power mode

In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.

A processor is described which includes a first pipeline, a second pipeline, and a control circuit. The first pipeline includes a first stage at which instruction results are committed to architected state. The first stage is separated from an issue stage of the first pipeline by a first number of stages. The second pipeline includes a second stage at which an exception is reportable, wherein the second stage is separated from the issue stage of the second pipeline by a second number of stages which is greater than the first number. The control circuit is configured to inhibit co-issuance of a first instruction to the first pipeline and a second instruction to the second pipeline if the first instruction is subsequent to the second instruction in program order.

Inhibiting of a co-issuing instruction in a processor having different pipeline lengths

A processor is contemplated which includes a queue configured to store one or more instructions and a control circuit coupled to the queue. The control circuit is configured to detect a replay of a first instruction due to a dependency on a load miss. In response to detecting the replay, the control circuit is configured to inhibit issuance of the one or more instructions in the queue to one or more pipelines of the processor. A carrier medium comprising one or more data structures representing the processor are also contemplated, as are a method of detecting the replay and inhibiting issuance of instructions in the queue in response to detecting the replay.

Power consumption reduction in a pipeline by stalling instruction issue on a load miss

A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.

Mechanism for processing speculative LL and SC instructions in a pipelined processor

An integrated circuit includes at least a first fuse and at least a first processor. Each fuse is in either a conductive state or a non-conductive state. The first processor is configured to operate at one of at least a first issue rate or a second issue rate responsive to the state of the first fuse. The first issue rate is lower than the second issue rate. In another embodiment, the first processor is configured to execute fewer instructions in a period of time responsive to a first state of the conductive state or the non-conductive state of the first fuse than the first processor is configured to execute in the period of time responsive to a second state of the first fuse. A method includes: (i) determining if an integrated circuit comprising at least one processor has a performance rating that exceeds a government-imposed export restriction; and (ii) in response to the performance rating exceeding the export restriction, blowing at least one fuse on the integrated circuit. The processor responds to a blown state of the fuse by executing, during use, fewer instructions per period of time than the processor would otherwise execute.

Limiting performance in an integrated circuit to meet export restrictions

An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline. The control circuit is configured to update the second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline. Replay may be signaled for a given instruction at the first stage. In response to a replay of a second instruction, the control circuit is configured to copy a contents of the second scoreboard to the first scoreboard. In various embodiments, additional scoreboards may be used for detecting different types of dependencies.

Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard

Growing community of inventors

Cupertino, CA, United States of America

Tse-Yu Yeh