Toyokazu Nakamura

This inventor holds 8 USPTO granted patents. Top assignees: Nec Corporation, Sanyo Chemical Industries, Ltd.. Active years: 1990-2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Toyokazu Nakamura. Retrieved from https://idiyas.com/inventor/toyokazu-nakamura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 8

% Patents Active = 100.0

Average Co-Inventor Count = 2.4

ph-index = 5

Forward Citations = 128(Granted Patents)

Company Filing History:

Sanyo Chemical Industries, Ltd.

patents

where one patent can have more than one assignee

Years Active: 1990-2001

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8 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6188785 - Pattern inspecting apparatus and inspecting method (2001-02-13),

2. 6177681 - Apparatus method for testing opening state for hole in semiconductor device (2001-01-23),

3. 5949900 - Fine pattern inspection device capable of carrying out inspection (1999-09-07),

4. 5703492 - System and method for fault analysis of semiconductor integrated circuit (1997-12-30),

5. 5548211 - Dynamic fault imaging system using electron beam and method of analyzing (1996-08-20),

6. 5521516 - Semiconductor integrated circuit fault analyzing apparatus and method (1996-05-28),

7. 5422498 - Apparatus for diagnosing interconnections of semiconductor integrated (1995-06-06),

8. 4921632 - Liquid crystal compounds and compositions (1990-05-01),

Title: The Innovative Contributions of Toyokazu Nakamura

Introduction

Toyokazu Nakamura is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of eight patents. His work focuses on enhancing the efficiency and effectiveness of semiconductor devices through innovative inspection and testing methods.

Latest Patents

Nakamura's latest patents include a pattern inspecting apparatus and an inspecting method. This invention utilizes an image signal from a large number of patterns on an LSI wafer, which is processed using a CMOS image sensor chip. The system incorporates a one-dimensional CMOS photodiode array, an analog-to-digital conversion circuit, a memory circuit, and a processing circuit. By employing a defect detection algorithm, the apparatus can extract defect images without relying on a normal inspection pattern, allowing for high-speed processing and miniaturization of the apparatus.

Another notable patent is the apparatus method for testing the opening state of a hole in a semiconductor device. This testing apparatus features a laser light radiating system that targets a hole formed in the insulating layer of a semiconductor device. The system detects photoelectrons emitted through the hole when irradiated with laser light, which is tailored based on the work functions of the materials involved. This innovative approach enhances the accuracy of testing the conductive layer beneath the insulating layer.

Career Highlights

Throughout his career, Toyokazu Nakamura has worked with notable companies

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]