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For the Inventor, By the Inventor

San Jose, CA, United States of America

Torsten Partsch

This inventor holds 25 USPTO granted patents and 16 published patent applications and 1 EPO patent, primarily in Dynamic Random Access Memory. Top assignee: Rambus Inc.. Active years: 2015-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Torsten Partsch. Retrieved from https://idiyas.com/inventor/torsten-partsch-ddz10c0m

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 25 

% Patents Active = 100.0

 

Average Co-Inventor Count = 1.7

ph-index = 2

Forward Citations = 14(Granted Patents)


Company Filing History:

goldMedal25 out of 2,959 
 
Rambus Inc.
 patents

Years Active: 2015-2026

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Areas of Expertise:
Dynamic Random Access Memory
DRAM Architecture
Data Destruction
Memory Reliability
Low Latency
Quad-Channel DRAM
Buffered Memory
Memory Scrubbing
Row Hammer Mitigation
Data Rate Alignment
Programmable Data-to-Clock Ratio
Multi-Chip Package
25 patents (USPTO):Explore Patents
1. 12730587 - Joint command dynamic random access memory (DRAM) apparatus and methods (2026-09-08),
2. 12694922 - Data destruction via dram refresh suppression (2026-07-28),
3. 12625799 - Memory device with staggered access (2026-05-12),
4. 12619534 - Interconnect based address mapping for improved reliability (2026-05-05),
5. 12610862 - Reliability for DRAM device stack (2026-04-21),
6. 12578863 - Low latency dynamic random access memory (DRAM) architecture with dedicated read-write data paths (2026-03-17),
7. 12566557 - DRAM refresh control with master wordline granularity of refresh intervals (2026-03-03),
8. 12499966 - Dynamic, random-access memory with hidden memory scrubbing (2025-12-16),
9. 12431182 - Row hammer mitigation (2025-09-30),
10. 12393531 - Quad-channel DRAM (2025-08-19),
11. 12374388 - Buffered dynamic random access memory device (2025-07-29),
12. 12230362 - Memory component with programmable data-to-clock ratio (2025-02-18),
13. 12229435 - Memory component with input/output data rate alignment (2025-02-18),
14. 12211583 - Data-buffer controller/control-signal redriver (2025-01-28),
15. 12135901 - Joint command dynamic random access memory (DRAM) apparatus and methods (2024-11-05),

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Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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