Low latency dynamic random access memory (dram) architecture with dedicated read-write data paths

Abstract

Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, a dynamic random access memory (DRAM) device is disclosed. The DRAM device includes memory core circuitry including an array of DRAM storage cells organized into bank groups. Each bank group includes multiple banks, where each of the multiple banks includes addressable columns of DRAM storage cells. The DRAM device includes signal interface circuitry having dedicated write data path circuitry and dedicated read data path circuitry. Selector circuitry, for a first memory transaction, selectively couples at least one of the addressable columns of DRAM storage cells to the dedicated read data path circuitry or the dedicated write data path circuitry.