logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12229435 B1

PDFFull Text
Date of Patent:
Feb. 18, 2025

Filed:

Jan. 15, 2024

Memory component with input/output data rate alignment

Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

John Eric Linstadt, Palo Alto, CA (US);

Torsten Partsch, San Jose, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:

Charles Shemwell

Primary Examiner:

Henry Tsai

Assistant Examiner:

Christopher A Daley

Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/16 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
G06F 3/0655 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 13/1668 (2013.01); G11C 7/06 (2013.01); G11C 7/1057 (2013.01); G11C 7/106 (2013.01); G11C 7/1066 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 7/22 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); H01L 25/0657 (2013.01); G06F 2213/16 (2013.01); G11C 7/1015 (2013.01); G11C 2207/107 (2013.01); G11C 2207/2272 (2013.01); G11C 2207/2281 (2013.01); G11C 2207/229 (2013.01); H01L 2225/06541 (2013.01);
Abstract

First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

Find Patent Forward Citations

Quick Actions:

Ware, Frederick. (2025). Memory component with input/output data rate alignment (U.S. Patent No. 12229435). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12229435

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…