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For the Inventor, By the Inventor

Sunnyvale, CA, United States of America

Tomer Eliash

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This inventor holds 27 USPTO granted patents and 14 published patent applications and 1 EPO patent, primarily in Memory Systems. Top assignees: Micron Technology Incorporated, Western Digital Technologies, Inc., Sandisk Technologies Inc.. Active years: 2021-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tomer Eliash. Retrieved from https://idiyas.com/inventor/tomer-eliash

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27 

% Patents Active = 92.6

 

Average Co-Inventor Count = 2.4

ph-index = 3

Forward Citations = 34(Granted Patents)


Location History:

  • San Jose, CA (US) (2021)
  • Sunnyvale, CA (US) (2021 - 2024)

Company Filing History:

goldMedal16 out of 39,222 
 
Micron Technology Incorporated
 patents
silverMedal6 out of 5,429 
 
Western Digital Technologies, Inc.
 patents
bronzeMedal5 out of 4,955 
 
Sandisk Technologies Inc.
 patents

Years Active: 2021-2026

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Areas of Expertise:
Dynamic Memory Operations
Memory Device Health Monitoring
Programming Operation Sequence
Underfill Detection
Asynchronous Power Loss
Read Error Handling
NAND Read Disturb Mitigation
Non-Volatile Memory
Peak Power Reduction
Thermal Region Tags
Physical Defect Detection
Address Table Cache Management
27 patents (USPTO):Explore Patents
1. 12754680 - Dynamic memory operations based on host profile (2026-10-06),
2. 12731656 - Memory device health monitoring and dynamic adjustment of device parameters (2026-09-08),
3. 12704970 - Managing allocation of sub-blocks in a memory sub-system (2026-08-11),
4. 12704956 - Underfill detection for memory systems (2026-08-11),
5. 12704955 - Managing programming operation sequence in a memory sub-system (2026-08-11),
6. 12633360 - Managing asynchronous power loss in a memory device (2026-05-19),
7. 12625767 - Storing status information using redundant columns (2026-05-12),
8. 12625622 - Selectively disabling memory devices (2026-05-12),
9. 12585388 - Selectively enabling valley track for reading data (2026-03-24),
10. 12444475 - Reducing read error handling operations during power up of a memory device (2025-10-14),
11. 12373116 - Dynamic read retry voltage sequences in a memory subsystem (2025-07-29),
12. 12314590 - Incomplete superblock management for memory systems (2025-05-27),
13. 12242722 - Underfill detection for memory systems (2025-03-04),
14. 12106812 - Detecting a memory write reliability risk without using a write verify operation (2024-10-01),
15. 12067255 - Error detection for programming single level cells (2024-08-20),

Title: The Innovative Mind of Tomer Eliash

Introduction: Tomer Eliash, a talented inventor based in Sunnyvale, CA, is known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Tomer Eliash holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his expertise in cutting-edge technologies.

Career Highlights: With a background in computer science and engineering, Tomer Eliash has worked for top tech companies in Silicon Valley, where he has led teams in developing innovative solutions that have revolutionized the industry.

Collaborations: Throughout his career, Tomer Eliash has collaborated with leading researchers and engineers from renowned universities and research institutions, fostering a culture of creativity and excellence in his projects.

Conclusion: Tomer Eliash continues to push the boundaries of technology with his inventive spirit and dedication to creating solutions that shape the future of innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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