Micron Technology Incorporated

Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Tomer Eliash

Yu-Chung Lien

Huai-Yuan Tseng

Eran Sharon

Alexander Bazarsky

Ariel Navon

Zhenming Zhou

Evgeny Mekhanik

Shay Benisty

Deepanshu Dutta

Jiahui Yuan

Mark Murin

Hua-Ling Cynthia Hsu

Alex Bazarsky

David Rozman

Sead Zildzic, Jr

Swaroop Kaza

Yair Chasdai

Dongxiang Liao

Barak Goldberg

A boot-up read pattern data structure is maintained. Each entry of the boot-up read pattern data structure comprises a boot-up read pattern associated with a respective power cycle event and a dummy boot-up read pattern flag. The dummy boot-up read pattern flag indicates that the boot-up read pattern has been consecutively used during boot-up. Storing, in a new entry of the boot-up read pattern data structure, a current boot-up read pattern associated with a respective power cycle event for each power cycle event. The current boot-up read pattern with a previous boot-up read pattern associated with a latest entry of the boot-up pattern data structure is compared. A dummy boot-up read pattern flag of the new entry is updated responsive to the comparing the current boot-up read pattern and the previous boot-up read pattern.

Reducing read error handling operations during power up of a memory device

Methods, systems, and apparatuses include determining to apply a read retry operation to a portion of memory. The likelihood of a read retry timeout meeting a threshold is determined. A reverse trim setting is selected in response to determining the likelihood of the read retry timeout meets the threshold. The read retry operation is executed using the selected trim setting.

Dynamic read retry voltage sequences in a memory subsystem

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide superblock management based on memory component reliabilities.

Incomplete superblock management for memory systems

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.

Underfill detection for memory systems

Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.

Detecting a memory write reliability risk without using a write verify operation

Methods, systems, and devices for error detection for programming single level cells of a memory system are described. The memory system may receive a write command for writing data to a block of memory cells and generate a write voltage to write the data to the block of memory cells. The memory system may compare the write voltage to a reference voltage and determine whether the write voltage satisfies a threshold tolerance associated with the reference voltage. The memory system may generate signaling indicating an error associated with writing the data to the block of memory cells, based on determining that the write voltage does not satisfy the threshold tolerance.

Error detection for programming single level cells

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide superbkock management based on memory component reliabilities.

Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.

Sub-block programming mode with multi-tier block

Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.

Efficient read of NAND with read disturb mitigation

A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.

Negative bit line biasing during quick pass write programming

In the context of data storage, an approach to pre-fetching data prior to a read request involves receiving a read request and a next read request, and updating metadata corresponding to the read request with a next data storage address corresponding to the next read request. Responsive to again receiving the read request at a later time, the next data storage address can be read from the read request metadata and the next data can be pre-fetched from the next data storage address in advance of processing a following read request. Furthermore, the next data can be pre-fetched during read queue idle time and stored in a cache buffer, in anticipation of another incoming next read request, responsive to which the next data can be returned to the host from the buffer rather than from a read of non-volatile memory.

Enhanced read-ahead capability for storage devices

A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in a plurality of planes. The apparatus also includes a control circuit coupled to the word lines and the bit lines and configured to determine whether a program operation of the memory cells involves all of the plurality of planes. In response to the program operation of the memory cells not involving all of the plurality of planes, the control circuit adjusts at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation based on a quantity of the plurality of planes associated with the memory cells being program-verified in the program operation.

Memory apparatus and method of operation using plane dependent ramp rate and timing control for program operation

Methods and apparatus for use with non-volatile memory (NVM) arrays having single-level cell (SLC) layers and multi-level cell (MLC) layers, such as triple-level cell (TLC) layers, provide for a coupled SLC/MLC write operation where SLC write protection is combined into a MLC write flow. In an illustrative example, data is written concurrently to SLC and TLC. The SLC data provides a backup for the TLC data in the event the TLC data is defective. The TLC data is verified using, for example, write verification. If the data is successfully verified, the SLC block can be erased or otherwise overwritten with new data. If not, the SLC block can be used to recover the data for storage in a different TLC block. The coupled SLC/MLC write operation may be performed in conjunction with a quick pass write (QPW).

Non-volatile memory array with write failure protection for multi-level cell (MLC) storage elements using coupled writes

Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

Peak power reduction management in non-volatile storage by delaying start times operations

A method, device, and system for improving read performance in frequently changing device temperature conditions through detecting thermal region tags and thermal region outliers in a memory device. A plurality of thermal regions may be configured for the memory device. A first temperature may be measured corresponding to opening a storage block of the memory device for programming. A second temperature may then be measured corresponding to closing the storage block for programming. A range between the first temperature and the second temperature may be determined. The range may span N&#x2265;2 of the thermal regions. Finally, the storage block may be assigned to a thermal region that includes the second temperature, on condition that N satisfies a threshold.

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Sunnyvale, CA, United States of America

Tomer Eliash