Tohru Furuyama

This inventor holds 49 USPTO granted patents, primarily in Dynamic Memory Technology. Top assignee: Kabushiki Kaisha Toshiba. Active years: 1987-2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tohru Furuyama. Retrieved from https://idiyas.com/inventor/tohru-furuyama

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 49

% Patents Active = 98.0

Average Co-Inventor Count = 1.5

ph-index = 17

Forward Citations = 842(Granted Patents)

Location History:

Kanagawa, JP (1991)
South Burlington, VT (US) (1997 - 1999)
Tokyo, JP (1987 - 2002)

Company Filing History:

49 out of 53,262

Kabushiki Kaisha Toshiba

patents

Years Active: 1987-2002

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Areas of Expertise:

Dynamic Random Access Memory

Semiconductor Memory

Memory Circuit

Screening Test

Bias Voltage Generation

Clock Synchronous Type DRAM

Memory Cell Unit

Static Random Access Memory

Test Method

Semiconductor Device

Cache Memory

RAS and CAS Signals

49 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6381186 - Dynamic random access memory (2002-04-30),

2. 6317366 - Dynamic random access memory (2001-11-13),

3. 6307796 - Dynamic random access memory (2001-10-23),

4. RE37184 - Semiconductor memory and screening test method thereof (2001-05-22),

5. 6166975 - Dynamic random access memory (2000-12-25),

6. 616697 - Dynamic random access memory (2000-12-26),

7. 6101148 - Dynamic random access memory (2000-08-08),

8. 5890186 - Memory circuit with built-in cache memory (1999-03-30),

9. 5754481 - Clock synchronous type DRAM with latch (1998-05-19),

10. 5673229 - Dynamic random access memory (1997-09-30),

11. 5659507 - Clock synchronous type DRAM with data latch (1997-08-19),

12. 5568436 - Semiconductor device and method of screening the same (1996-10-22),

13. 5553024 - Semiconductor memory utilizing RAS and CAS signals to control the (1996-09-03),

14. 5532963 - Semiconductor memory and screening test method thereof (1996-07-02),

15. 5525820 - Semiconductor memory cell (1996-06-11),

Title: Innovator Spotlight: Tohru Furuyama

Introduction: Tohru Furuyama is a notable inventor based in Tokyo, Japan, recognized for his substantial contributions to the field of semiconductor technology. He holds an impressive portfolio of 49 patents, showcasing his expertise and innovation in the development of advanced memory systems.

Latest Patents: Furuyama's recent patents focus on dynamic random access memory (DRAM) technology. One of his noteworthy inventions describes a dynamic random access memory that utilizes multiple dynamic memory cells organized in rows and columns. It features a word line selecting circuit for selecting rows based on internal address signals and includes a sophisticated control circuit that manages the driving of word lines during voltage stress tests. Another significant invention involves a semiconductor memory device that comprises a memory cell equipped with a transfer N-channel MOS transistor. This memory device incorporates a charge pump circuit generating an internal power supply voltage and a decoder circuit which enhances the operational efficiency of the memory system.

Career Highlights: Furuyama is currently affiliated with Kabushiki Kaisha Toshiba, a leading company in the technology sector. His role involves pioneering developments in semiconductor memory technology, a critical area in the progression of electronic devices.

Collaborations: Throughout his career, Furuyama has collaborated with several distinguished professionals, including his coworkers Junichi Okamura and Natsuki Kushiyama. Their combined expertise fosters an environment of innovation that drives advancements within their projects.

Conclusion: Tohru Furuyama's contributions to dynamic random access memory technology have established him as a prominent figure in the field of semiconductor innovation. With a remarkable track record and ongoing collaborations, his work continues to influence the technological landscape significantly.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]