Dynamic random access memory

Abstract

A semiconductor memory device includes a memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the memory cell, a charge pump circuit generating an internal power supply voltage which is boosted up from a power supply voltage, and outputting the internal power supply voltage, and a decoder circuit which receives address signals and has a P-channel MOS transistor for receiving the internal power supply voltage, the decoder circuit generating a word line selecting signal. Also, the semiconductor memory device includes a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a first MOS transistor and a second MOS transistor, the first MOS transistor having a first current path, a first end of the first current path being connected to a first node having the internal power supply voltage, a second end of the first current path being connected to the word line and a gate which is controlled in accordance with the word line selecting signal, the second MOS transistor having a second current path, a first end of the second current path being connected to the first MOS transistor, a second end of the second current path being connected to a predetermined potential lower than the internal power supply voltage, wherein the charge pump circuit outputs the internal power supply voltage for a first period in which at least the P-channel MOS transistor is in an ON state and a second period in which at least the first MOS transistor is in an ON state.