The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 1999
Filed:
Jul. 17, 1997
Katsuhiko Sato, Yokohama, JP;
Shinji Miyano, Yokohama, JP;
Tomoaki Yabe, Kawasaki, JP;
Tohru Furuyama, South Burlington, VT (US);
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
When data stored in a memory cell of a memory cell array is written into cache memory, a write signal LW is set at an 'H' level. The write signal LW is input into a data-line pair initialization select circuit via an initialization control circuit, and a signal EQE is set at an 'H' level in all columns. A data-line pair initialization circuit then sets the potential of the data-line pairs in all columns at the same level. When the write signal LW is input to a transfer gate via a transfer gate control circuit, the transfer gates in all columns are turned ON. The delay time of the transfer gate control circuit is the same as or greater than the delay time of the initialization control.