Taipei, Taiwan

Tien-Fan Ou

This inventor holds 10 USPTO granted patents and 3 published patent applications. Top assignees: Macronix International Co., Ltd., United Microelectronics Corp.. Active years: 2010-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tien-Fan Ou. Retrieved from https://idiyas.com/inventor/tien-fan-ou

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 10 

% Patents Active = 70.0

Average Co-Inventor Count = 3.0

ph-index = 3

Forward Citations = 29(Granted Patents)


Location History:

  • Hsinchu, TW (2010 - 2012)
  • Taipei, TW (2011 - 2013)
  • New Taipei, TW (2017 - 2018)

Company Filing History:


Years Active: 2010-2018

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10 patents (USPTO):Explore Patents

Title: Tien-Fan Ou: Innovator in Non-Volatile Memory Technologies

Introduction

Tien-Fan Ou is a prominent inventor based in Taipei, Taiwan. He has made significant contributions to the field of non-volatile memory devices, holding a total of 10 patents. His work has advanced the technology used in memory devices, making them more efficient and effective.

Latest Patents

Among his latest patents is a non-volatile memory device and operation method. This invention provides a non-volatile memory device that includes a source region, a drain region, a channel region, a floating gate, an enhance hot carrier injection gate, and an erasing gate. The floating gate is strategically placed on the channel region and the source region, with a first dielectric layer in between. The enhance hot carrier injection gate, which has an L-shaped cross-section, is positioned on the floating gate and the substrate. Additionally, a second dielectric layer is situated between the enhance hot carrier injection gate and the floating gate, while a fourth dielectric layer is placed between the enhance hot carrier injection gate and the substrate. The erasing gate is located on the drain region, with a third dielectric layer in between the erasing gate and the substrate.

Another notable patent is related to a composite impurity scheme for memory technologies. This integrated circuit features a memory array that includes diffusion bit lines with composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures at the cross-points. The composite impurity diffusion bit lines provide source and drain terminals on opposing sides of the channel regions, ensuring high conductivity, good depth, and steep doping profiles, even with channel region critical dimensions below 50 nanometers.

Career Highlights

Tien-Fan Ou has worked with notable companies in the semiconductor industry, including Macronix International Co., Ltd. and United Microelectronics Corporation. His experience in these organizations has allowed him to develop and refine his innovative ideas in memory technology.

Collaborations

Throughout his career, Tien-Fan Ou has collaborated with talented individuals such as Wen-Jer Tsai and Jyun-Siang Huang. These collaborations have contributed to the advancement of his research and inventions.

Conclusion

Tien-Fan Ou is a distinguished inventor whose work in

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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