The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Apr. 01, 2014
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Wei Lee, New Taipei, TW;

Tien-Fan Ou, New Taipei, TW;

Jyun-Siang Huang, Chiayi, TW;

Chien-Hung Liu, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/112 (2006.01); G11C 16/04 (2006.01); H01L 27/11568 (2017.01); H01L 21/265 (2006.01); H01L 29/10 (2006.01); H01L 29/167 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0491 (2013.01); H01L 21/26513 (2013.01); H01L 27/11568 (2013.01); H01L 29/1045 (2013.01); H01L 21/2658 (2013.01); H01L 21/26586 (2013.01); H01L 29/167 (2013.01);
Abstract

An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.


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