Teruo Uemura

Title: Teruo Uemura: Innovator in Semiconductor Technology

Introduction

Teruo Uemura is a prominent inventor based in Kawasaki, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 5 patents. His work focuses on enhancing the performance and efficiency of semiconductor devices.

Latest Patents

Uemura's latest patents include innovative designs for semiconductor devices. One notable patent describes a semiconductor device that integrates an n-channel MOSFET, a p-channel MOSFET, and a nonvolatile memory cell on the same semiconductor substrate. This design allows for improved functionality, as the nonvolatile memory cell is strategically formed on the substrate, with the n-channel MOSFET in a p-type well region and the p-channel MOSFET in an n-type well region. Another significant patent involves a semiconductor memory device that features a non-volatile memory cell array. This device includes enhancement type load transistors with a threshold voltage that differs from that of the enhancement type transistors in the peripheral circuit, thereby increasing the writing speed of the memory cells.

Career Highlights

Teruo Uemura is currently associated with Kabushiki Kaisha Toshiba, where he continues to push the boundaries of semiconductor technology. His work has been instrumental in developing advanced memory devices that meet the growing demands of modern electronics.

Collaborations

Uemura has collaborated with notable colleagues, including Naoki Hanada and Takahide Mizutani. Their combined expertise has contributed to the successful development of innovative semiconductor solutions.

Conclusion

Teruo Uemura's contributions to semiconductor technology are noteworthy, with a focus on enhancing device performance through innovative designs. His patents reflect a commitment to advancing the field, making him a significant figure in the world of inventions.