Kabushiki Kaisha Toshiba

Teruo Uemura

Naoki Hanada

Takahide Mizutani

Masayuki Yoshida

Yukihiro Saeki

Osamu Matsumoto

Kazuyoshi Shinada

Tomohisa Shigematsu

Kenji Toyoda

Nobuyoshi Chida

Hiroyuki Takamura

Tatsuo Mori

Yukio Kawase

An n-channel MOSFET, a p-channel MOSFET and a nonvolatile memory cell are provided for the same semiconductor substrate. The nonvolatile memory cell is formed on the semiconductor substrate, the n-channel MOSFET is formed in a p-type well region of the semiconductor substrate, and the p-channel MOSFET is formed in an n-type well region of the semiconductor substrate.

Semiconductor device wherein n-channel MOSFET, p-channel MOSFET and

A semiconductor memory device comprises a non-volatile memory cell array having a plurality of memory cells, enhancement type load transistors having a threshold voltage, and at least one peripheral circuit, such as level shifters, a column decoder, etc., including enhancement type transistors having a threshold voltage. For increasing the writing speed of the memory cells, the threshold voltage of the enhancement type load transistors is set so that it is different from that of the enhancement type transistors of the peripheral circuit. For example, the threshold voltage of the enhancement type load transistors is lower than that of the enhancement type transistors of the peripheral circuit.

Semiconductor memory device including nonvolatile memory cells,

A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film and a gate oxide film on a semiconductor substrate, depositing a first conductive layer on an entire surface of the resultant structure, selectively etching the first conductive layer located in a region other than an element region, depositing a second conductive layer on an entire surface of the resultant structure, and etching the first conductive layer and the second conductive layer using the same mask to form a plurality of floating gates by the first conductive layer and to form a plurality of control gates by the second conductive layer, wherein the step of selectively etching the first conductive layer includes the first etching step of forming cell slits for separating the plurality of floating gates from each other and the second etching step of forming removed regions each of which includes only one end of each of the plurality of control gates.

Manufacturing method for a floating gate semiconductor memory device by

An E.sup.2 PROM and an EPROM are formed on the same substrate. An E.sup.2 PROM memory cell has a floating gate and a control gate. A tunnel insulating film is formed between the floating gate and source/drain regions, thereby constituting a memory cell of an 'FLOTOX' type. An EPROM memory cell has a floating gate and a control gate, thus constituting a memory cell of an 'SAMOS' type.

Semiconductor device having E.sup.2 PROM and EPROM in one chip

Growing community of inventors

Kawasaki, Japan

Teruo Uemura