Santa Clara, CA, United States of America

Teh-Yi J Chen

This inventor holds 3 USPTO granted patents. Top assignees: Signetics, North American Philips Corp, Signetics Division. Active years: 1986-1988.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Teh-Yi J Chen. Retrieved from https://idiyas.com/inventor/teh-yi-j-chen-v9fdk4cl

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.4

ph-index = 3

Forward Citations = 52(Granted Patents)


Company Filing History:


Years Active: 1986-1988

Loading Chart...
3 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Teh-Yi J Chen in Semiconductor Technology

Introduction

Teh-Yi J Chen is a notable inventor based in Santa Clara, California, recognized for his significant contributions to the field of semiconductor technology. With a total of three patents to his name, Chen's work focuses on enhancing the efficiency and efficacy of field-effect transistors, which are critical components in modern electronic devices.

Latest Patents

Among his latest innovations is a "Method of fabricating field-effect transistor utilizing improved gate." This patent outlines a two-step procedure for creating gate sidewall spacers using protective materials like silicon nitride to prevent gate-electrode oxidation, significantly enhancing the reliability of the transistor. The first step involves the conformal deposition of insulating material, which is largely removed, leaving small spacer portions adjacent to the sidewalls of a doped non-monocrystalline semiconductor layer, which will become the gate electrode. The second step includes an oxidizing heat treatment to increase the thickness of these spacer portions, effectively preventing significant gate dielectric encroachment and avoiding electrical shorts.

Another important patent is titled "Method of manufacturing an insulated gate field effect device." This patent describes a method for fabricating insulated gate field effect transistors in both NMOS and CMOS configurations. The process emphasizes the creation of source and drain regions with lightly doped extensions, allowing for a self-aligned manufacturing process, which ultimately results in devices in accordance with this innovative methodology.

Career Highlights

Teh-Yi J Chen has had an illustrious career, having worked with esteemed companies such as Signetics and North American Philips Corporation's Signetics Division. His experience at these organizations has significantly influenced his inventive endeavors and contributions to the semiconductor industry.

Collaborations

Throughout his career, Chen has collaborated with esteemed colleagues, including Anjan Bhattacharyya and William T Stacy. These partnerships have fostered an environment of innovation and expertise in developing advanced semiconductor technologies.

Conclusion

Teh-Yi J Chen's contributions to the field of semiconductor technology and his innovative patents continue to shape advancements in electronic devices. Through his work, he exemplifies the spirit of innovation that drives the industry forward, making him a prominent figure in the realm of inventions and patent development.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…