Company Filing History:

10 out of 29,279

Texas Instruments Corporation

patents

6 out of 38,002

Micron Technology Incorporated

where one patent can have more than one assignee

Years Active: 1995-2016

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16 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9406404 - Column redundancy system for a memory array (2016-08-02),

2. 8743650 - Block repair scheme (2014-06-03),

3. 8223583 - Row addressing (2012-07-17),

4. 8068380 - Block repair scheme (2011-11-29),

5. 7933162 - Row addressing (2011-04-26),

6. 7515501 - Memory architecture having local column select lines (2009-04-07),

7. 6373745 - Semiconductor memory cell and semiconductor memory device (2002-04-16),

8. 6249472 - Semiconductor memory device with antifuse (2001-06-19),

9. 6038191 - Circuit for reducing stand-by current induced by defects in memory array (2000-03-14),

10. 5875194 - Repairing efficiency by gray code (1999-02-23),

11. 5689465 - Semiconductor memory device and defective memory cell correction circuit (1997-11-18),

12. 5594279 - Semiconductor device having shield wiring for noise suppression (1997-01-14),

13. 5550394 - Semiconductor memory device and defective memory cell correction circuit (1996-08-27),

14. 5485425 - Semiconductor memory device having redundant column and operation method (1996-01-16),

15. 5461586 - Self-timed redundancy circuit (1995-10-24),

Title: The Innovative Journey of Takumi Nasu

Introduction: Takumi Nasu, an accomplished inventor based in Tsuchiura, Japan, has made significant contributions to the field of memory systems with a remarkable portfolio of 16 patents. His inventive spirit and dedication to innovation have led to groundbreaking developments in memory arrays and repair schemes that enhance the reliability and efficiency of modern technology.

Latest Patents: Nasu's latest patents include two notable inventions: the "Column Redundancy System for a Memory Array" and a "Block Repair Scheme". The first patent describes a memory array that comprises a main memory array and a redundant memory array, featuring redundant memory organized in replacement units. This ensures that memory from the main array can be mapped efficiently, with I/O groups that provide flexibility and redundancy. The second patent presents a novel approach to block repair in memory arrays, enabling the mapping of non-redundant rows to distributed redundant rows in the event of block failures, thereby maintaining system integrity and enhancing performance.

Career Highlights: Throughout his career, Takumi Nasu has worked for prominent companies such as Texas Instruments Corporation and Micron Technology Incorporated. His efforts have yielded pivotal advancements in the semiconductor industry, solidifying his reputation as a key player in memory technology innovation.

Collaborations: Nasu's innovative journey has also been marked by collaborations with talented individuals, including his coworkers Takuya Nakanishi and Hidetoshi Iwai. These partnerships have fostered a stimulating environment for creative problem-solving and have contributed to the successful realization of several of Nasu’s patents.

Conclusion: Takumi Nasu's remarkable contributions to the field of memory systems through his 16 patents exemplify his status as a leader in innovation. His latest inventions reflect a deep understanding of complex memory architectures, and his collaborations only enhance his pursuit of excellence. As technology continues to evolve, Nasu's work will undoubtedly play a critical role in shaping the future of memory solutions.

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