The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2002
Filed:
Mar. 21, 2001
Yoritaka Saito, Tsukuba, JP;
Hiroshi Ikeda, Edosaki-machi, JP;
Takumi Nasu, Tsuchiura, JP;
Kohsuke Ikeda, Ryugasaki, JP;
Yoshinobu Matsumoto, Ushiku, JP;
Satoshi Nakayama, Ami-machi, JP;
Yasuhito Ichimura, Kasama, JP;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The objective of this invention is to reduce the layout area while guaranteeing data retention stability in a static type semiconductor memory cell. This SRAM cell is constituted with two MOS transistors and and one inverter circuit . The source terminal of PMOS transistor is connected to bit line (BL), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to word line (WL). The source tenninal of NMOS transistor is connected to a supply voltage terminal that provides low-level reference potential V (for example, zero volts), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to the output terminal o inverter circuit . The input terminal of inverter circuit is connected to data storage node (Na).