Taipei, Taiwan

Ta-Wei Wang

This inventor holds 17 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2007-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ta-Wei Wang. Retrieved from https://idiyas.com/inventor/ta-wei-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 82.4

Average Co-Inventor Count = 2.9

ph-index = 5

Forward Citations = 162(Granted Patents)


Company Filing History:


Years Active: 2007-2018

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17 patents (USPTO):Explore Patents

Title: Ta-Wei Wang: Innovator in Semiconductor Technology

Introduction

Ta-Wei Wang is a prominent inventor based in Taipei, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 17 patents. His work focuses on enhancing the performance and efficiency of semiconductor devices, particularly in the area of MOSFET transistors.

Latest Patents

One of his latest patents is titled "Defect-Free SiGe source/drain formation by epitaxy-free process." This invention involves MOSFET transistors that utilize localized stressors to improve carrier mobility. The design includes a gate electrode formed over a substrate, with a carrier channel region beneath it. The source/drain regions on either side of the channel feature an embedded stressor with a different lattice constant than the substrate. In this case, the substrate is silicon, while the embedded stressor is SiGe. The process includes implanting a portion of the source/drain regions with Ge to form the embedded stressor. Additionally, implanting carbon into these regions and subsequently annealing the substrate helps suppress dislocation formation, thereby enhancing device performance.

Another notable patent is for a "High performance CMOS device design." This semiconductor device features a gate that comprises a gate electrode and a gate dielectric. It also includes a spacer on the sidewall of the gate and a buffer layer with a first portion beneath the gate dielectric and a second portion adjacent to the spacer. The design ensures that the top surface of the second portion is recessed below that of the first portion, with a source/drain region aligned with the spacer. The buffer layer has a greater lattice constant than the underlying semiconductor substrate, which contributes to improved device functionality.

Career Highlights

Ta-Wei Wang is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His innovative work has positioned him as a key figure in advancing semiconductor technology.

Collaborations

He has collaborated with notable colleagues, including Chih-Hao Wang and Ching-Wei Tsai, contributing to various projects that push the boundaries of semiconductor research and development.

Conclusion

Ta-Wei Wang's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor in the field. His work continues to impact the performance of semiconductor devices, paving the way for future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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