Taiwan Semiconductor Manufacturing Comp. Ltd.

Ta-Wei Wang

Chih-Hao Wang

Ching-Wei Tsai

Shang-Chih Chen

Pang-Yen Tsai

Chih-Sheng Chang

Shih-Hsieng Huang

Chenming Hu

MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.

Defect-Free SiGe source/drain formation by epitaxy-free process

A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

High performance CMOS device design

A semiconductor device includes a gate stack; an air-gap under the gate stack; a semiconductor layer vertically between the gate stack and the air-gap; and a first dielectric layer underlying and adjoining the semiconductor layer. The first dielectric layer is exposed to the air-gap.

Process for fabricating silicon-on-nothing MOSFETs

Defect-free SiGe source/drain formation by epitaxy-free process

A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.

A strained channel transistor can be provided by combining a stressor positioned in the channel region with stressors positioned on opposite sides of the channel region. This produces increased strain in the channel region, resulting in correspondingly enhanced transistor performance.

MOS transistor with in-channel and laterally positioned stressors

An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature. An integrated circuit having high performance CMOS devices with low parasitic junction capacitance may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant.

High performance CMOS devices and methods for making same

A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.

High performance transistor with a highly stressed channel

A MOS device having reduced recesses under a gate spacer and a method for forming the same are provided. The MOS device includes a gate structure overlying the substrate, a sidewall spacer on a sidewall of the gate structure, a recessed region having a recess depth of substantially less than about 30 &#x212b; underlying the sidewall spacer, and a silicon alloy region having at least a portion in the substrate and adjacent the recessed region. The silicon alloy region has a thickness of substantially greater than about 30 nm. A shallow recess region is achieved by protecting the substrate when a hard mask on the gate structure is removed. The MOS device is preferably a pMOS device.

MOS devices with reduced recess on substrate surface

A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 10atoms/cmto about 10atoms/cmnitrogen. The MOSFET further includes a high-k dielectric material on the nitrided, non-high-k dielectric. The high-k dielectric preferably includes HfSiON, ZrSiON, or nitrided AlO. Embodiments further include asymmetric manufacturing techniques wherein core and peripheral integrated circuit areas are separately optimized.

Nitrogen treatment to improve high-k gate dielectrics

A method of making an integrated circuit chip is provided, which combines a smart grading implant with a diffusion retarding implant, e.g., to improve short channel effect controllability and improve dopant grading in the source/drain regions. Using a smart grading implant, a relatively low-energy high-dose implant is performed before a relatively low-energy high-dose implant. Hence, a relatively high-energy low-dose implant of ions is performed into a source/drain region of a substrate. A diffusion retarding implant is performed into the source/drain region of the substrate. Then after performing the high-energy low-dose implant and the diffusion retarding implant (together, overlapping, or separately), a relatively low-energy high-dose implant of ions is performed into the source/drain region of the substrate.

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Taipei, Taiwan

Ta-Wei Wang