Beaverton, OR, United States of America

Stephen S Pawlowski

This inventor holds 69 USPTO granted patents and 6 published patent applications, primarily in Memory Architecture (CPC class G06F). Top assignees: Intel Corporation, Micron Technology Incorporated, Intel Corportion. Active years: 1993-2026.

USPTO Granted Patents = 69 

% Patents Active = 92.8

Average Co-Inventor Count = 2.6

ph-index = 16

Forward Citations = 927(Granted Patents)

Forward Citations (Not Self Cited) = 883(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Aloha, OR (US) (1994)
  • Beaverton, US (1996)
  • Beaverton, OH (US) (1998)
  • Beaverton, OR (US) (1993 - 2024)

Company Filing History:


Years Active: 1993-2026

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Areas of Expertise:
Parity Cache
Memory Controller
RAID Reliability
Cache Systems
Data Transfer
Bus Architecture
Memory Protection
Pipelined Systems
Interrupt Management
Latency Reduction
Multi-Processor Systems
Peripheral Protocol
69 patents (USPTO):Explore Patents

Title: The Innovations of Stephen S. Pawlowski

Introduction

Stephen S. Pawlowski, an accomplished inventor based in Beaverton, OR, has made significant contributions to the field of memory technology. With a remarkable portfolio of 64 patents, he has been instrumental in advancing innovations that enhance memory management and data protection.

Latest Patents

Among his latest patents are two noteworthy inventions. The first is a "Memory controller for managing RAID information." This memory controller features a front-end portion that interfaces with a host, a central controller for data management, and a back-end portion for interfacing with memory devices. It is equipped with interface management circuitry that can direct memory access requests efficiently. The innovative aspect lies in its ability to cache data in multiple locations simultaneously, showcasing a sophisticated approach to memory management.

The second patent, "Memory device protection using interleaved multibit symbols," introduces a method to implement error correction and detection capabilities in dual in-line memory modules (DIMMs) that utilize memory chips with larger bus widths. By interleaving symbols among a set of codewords, this invention significantly enhances data integrity within memory devices, providing robust protection against errors.

Career Highlights

Stephen has had a remarkable career, having worked with industry giants such as Intel Corporation and Micron Technology Incorporated. His expertise in memory systems and architecture has been pivotal in developing cutting-edge technologies in the semiconductor field.

Collaborations

Throughout his career, Stephen has collaborated with notable individuals including Peter D. MacWilliams and Gurbir Singh. Their combined efforts have led to advancements in various aspects of memory technology, enriching the field with their innovative work.

Conclusion

Stephen S. Pawlowski exemplifies the spirit of innovation through his numerous patents and dedication to advancing memory technology. His contributions have not only solidified his reputation as a leading inventor but also continue to influence the future of memory management systems. With a strong foundation of collaboration and a passion for invention, his career serves as an inspiring model for aspiring inventors around the globe.

Profile summary based on public USPTO records.
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