Intel Corporation

Micron Technology Incorporated

Intel Corportion

Stephen S Pawlowski

Peter D MacWilliams

Gurbir Singh

Robert J Greiner

William S Wu

David Lawrence Hill

Donald D Parker

Nitin V Sarangdhar

Richard Cameron Murphy

Anton Korzh

Muthurajan Jayakumar

Daniel G Lau

Paolo Amato

Emanuele Confalonieri

Brent S Baxter

Michael W Rhodehamel

Patrick Alan Estep

Marco Sforzin

Konrad K Lai

Nicola Del Gatto

Mani Azimi

Patrick F Stolt

Jerzy B Kolinski

Tom Holman

Vincent J Zimmer

Mohan J Kumar

Andrew F Glew

David I Poisner

Mallik Bulusu

Jasmin Ajanovic

Robert Charles Swanson

John I Garney

Mahesh S Natu

Sridhar Lakshmanamurthy

Howard S David

Kirk D Brannock

Harshvardhan P Sharangpani

Darren L Abramson

Matthew A Fisch

Madhusudhan Rangarajan

Ernest T Tsui

Luiz M Franca-Neto

Dimitrios Ziakas

Douglas Raymond Moran

D Michael Bell

Sham M Datta

George R Hayek

Jeffrey E Smith

Mani Ayyar

Anthony L Chun

Keith M Self

Richard C Calderwood

Robert W Cone

Sunny C Huang

John Thomas Sprietsma

Dennis Bell

Russell J Wunderlich

Frank L Wildgrube

Bindi A Prasad

Kimberly C Weier

Len J Schultz

C Brendan Traw

Babak B Nikjou

Siva Simanapalli

Miles F Schwartz

John R Lindsley

Lee Snyder

Timothy W Kelly

Henry Schaechterle

David M Cowan

Kishore K Mishra

M Jayakumar

David E Ackelson

An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups. The memory controller comprises a plurality of memory access request/response buffer sets, and each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups.

Memory controller architecture

Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.

Cache bypass

A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.

Memory controller for managing raid information

Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.

Memory device protection using interleaved multibit symbols

The present disclosure techniques for implementing an apparatus, which includes processing circuitry that performs an operation based a target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple of data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.

Extended line width memory-side cache systems and methods

The present disclosure provides techniques for implementing a computing system that includes a processing sub-system, a memory sub-system, and one or more memory controllers. The processing sub-system includes processing circuitry that performs an operation based on a target data block and a processor-side cache coupled between the processing circuitry and a system bus. The memory sub-system includes a memory that stores data blocks in a memory array and a memory-side caches coupled between the memory channel and the system bus. The one or more memory controllers control caching in the processor-side cache based at least in part on temporal relationship between previous data block targeting by the processing circuitry and control caching in memory-side cache based at least in part on spatial relationship between data block storage locations in the memory channel.

Adaptive line width cache systems and methods

The present disclosure provides techniques for implementing an apparatus, which includes processing circuitry that performs an operation based on target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.

Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.

Initialization trace of a computing device

Systems and methods of operating a computing system may involve utilizing at least one of a peripheral protocol negotiation and a universal connector to determine a peripheral device protocol, and reconfiguring a computer device to accommodate that peripheral device protocol. Upon such a reconfiguration, the peripheral protocol negotiation may 'step aside', and one or more subsequent communications between a host computer and the peripheral device utilizing the peripheral device protocol may start.

Peripheral protocol negotiation

Method and apparatus for a filter micro-code accelerator are described.

Filter micro-coded accelerator

A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.

Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system

An amplifier has a band pass response. The band pass response may be set by setting corner frequencies of low pass filters.

Bandpass amplifier, method, and system

A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.

Enhanced highly pipelined bus architecture

Growing community of inventors

Beaverton, OR, United States of America

Stephen S Pawlowski