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For the Inventor, By the Inventor

Hillsboro, OR, United States of America

Sridhar Govindaraju

This inventor holds 18 USPTO granted patents and 3 published patent applications. Top assignee: Intel Corporation. Active years: 2010-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sridhar Govindaraju. Retrieved from https://idiyas.com/inventor/sridhar-govindaraju

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 18 

% Patents Active = 77.8

Average Co-Inventor Count = 3.1

ph-index = 3

Forward Citations = 21(Granted Patents)


Location History:

  • Portland, OR (US) (2021 - 2023)
  • Hillsboro, OR (US) (2010 - 2024)

Company Filing History:

goldMedal18 out of 56,322 
 
Intel Corporation
 patents

Years Active: 2010-2024

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18 patents (USPTO):Explore Patents
1. 12094780 - Techniques and configurations to reduce transistor gate short defects (2024-09-17),
2. 11978776 - Non-planar semiconductor device having conforming ohmic contacts (2024-05-07),
3. 11756833 - Techniques and configurations to reduce transistor gate short defects (2023-09-12),
4. 11705453 - Self-aligned gate endcap (SAGE) architecture having local interconnects (2023-07-18),
5. 11688792 - Dual self-aligned gate endcap (SAGE) architectures (2023-06-27),
6. 11605632 - Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls (2023-03-14),
7. 11380592 - Techniques and configurations to reduce transistor gate short defects (2022-07-05),
8. 11329138 - Self-aligned gate endcap (SAGE) architecture having endcap plugs (2022-05-10),
9. 11217582 - Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls (2022-01-04),
10. 11205708 - Dual self-aligned gate endcap (SAGE) architectures (2021-12-21),
11. 10847423 - Techniques and configurations to reduce transistor gate short defects (2020-11-24),
12. 10468305 - Techniques and configurations to reduce transistor gate short defects (2019-11-05),
13. 9761497 - Techniques and configurations to reduce transistor gate short defects (2017-09-12),
14. 9704798 - Using materials with different etch rates to fill trenches in semiconductor devices (2017-07-11),
15. 9281401 - Techniques and configurations to reduce transistor gate short defects (2016-03-08),

Title: The Innovative Journey of Sridhar Govindaraju

Introduction: Sridhar Govindaraju, a talented inventor based in Hillsboro, OR (US), has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Sridhar Govindaraju holds several patents in the areas of artificial intelligence, machine learning, and semiconductor technology, showcasing his expertise and creativity in these cutting-edge fields.

Career Highlights: With a background in engineering and a passion for pushing the boundaries of what is possible, Sridhar Govindaraju has had a successful career working for leading tech companies, where he has spearheaded projects that have revolutionized the industry.

Collaborations: Throughout his career, Sridhar Govindaraju has collaborated with top researchers, engineers, and scientists to bring his ideas to life, fostering a culture of innovation and excellence in all his projects.

Conclusion: Sridhar Govindaraju's relentless pursuit of innovation and his commitment to pushing the limits of technology make him a true pioneer in his field, with a legacy that will continue to inspire future generations of inventors.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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