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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12094780 B1

PDFFull Text
Date of Patent:
Sep. 17, 2024

Filed:

Jul. 19, 2023

Techniques and configurations to reduce transistor gate short defects

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sridhar Govindaraju, Hillsboro, OR (US);

Matthew J. Prince, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Schwabe, Williamson & Wyatt P.C.

Primary Examiner:

Patricia D Valenzuela

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); G06F 30/39 (2020.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/31053 (2013.01); H01L 21/32115 (2013.01); H01L 21/76805 (2013.01); H01L 21/7684 (2013.01); H01L 21/76895 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 21/823475 (2013.01); H01L 23/49838 (2013.01); H01L 23/5329 (2013.01); H01L 23/535 (2013.01); H01L 24/16 (2013.01); H01L 27/0886 (2013.01); H01L 29/42372 (2013.01); H01L 29/4238 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); G06F 30/39 (2020.01); H01L 21/823871 (2013.01); H01L 21/845 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/00 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

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