Hsinchu, Taiwan

Shyue-Ter Leu

This inventor holds 26 USPTO granted patents and 7 published patent applications, primarily in Semiconductor Packaging. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2017-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shyue-Ter Leu. Retrieved from https://idiyas.com/inventor/shyue-ter-leu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26 

% Patents Active = 100.0

Average Co-Inventor Count = 4.3

ph-index = 3

Forward Citations = 38(Granted Patents)


Company Filing History:


Years Active: 2017-2025

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Areas of Expertise:
Semiconductor Device
Packaging Substrate
Warpage Control
Thermal Dissipation
Delamination Prevention
Conductive Line
Integrated Fan-Out
Chip Package
Manufacturing Method
Polymer Layer
Structure Formation
Insulation Opening
26 patents (USPTO):Explore Patents

Title: **Innovations of Shyue-Ter Leu in Chip Package Structures**

Introduction

Shyue-Ter Leu is a prominent innovator based in Hsinchu, Taiwan, known for his significant contributions to the field of semiconductor packaging. With an impressive portfolio of 20 patents, his work focuses on advancements that enhance the efficiency and reliability of chip package structures. His innovative approaches continue to shape the industry and lead to groundbreaking developments.

Latest Patents

Among his latest patents, Shyue-Ter Leu has developed a method for forming a chip package structure. This invention details a chip package that includes a first chip structure with a substrate and an interconnect layer, alongside a second chip structure and conductive elements designed to optimize electrical connections. The robustness of the design is highlighted by the inclusion of a molding layer that encases critical components, ensuring durability and performance.

Another noteworthy patent involves a wafer-level package with a polymer layer delamination prevention design. This invention encompasses a substrate and multiple passivation layers, with a unique step structure that enhances the functionality and structural integrity of the polyester layer. By ensuring a firm engagement of the polymer layer with the step structure, this patent helps prevent delamination, a common issue in package integrity.

Career Highlights

Shyue-Ter Leu's career is marked by his dedication to semiconductor advancements, particularly through his work at Taiwan Semiconductor Manufacturing Company Ltd. His ability to innovate continuously has made him a vital contributor to his team and the field. His pursuit of technological excellence has helped enhance the performance capabilities of modern chip packaging.

Collaborations

Throughout his career, Shyue-Ter Leu has collaborated with notable professionals, including Shin-Puu Jeng and Po-Yao Lin. These partnerships emphasize the collective effort within the industry to push boundaries and create innovative solutions that meet the demands of the rapidly evolving semiconductor landscape.

Conclusion

Shyue-Ter Leu exemplifies the spirit of innovation in the semiconductor industry. His patents reflect a deep understanding of chip packaging technologies and a commitment to improving the quality and efficiency of electronic devices. As technology continues to evolve, contributions from inventors like Leu will be essential in driving the next wave of advancements in this crucial field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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