Taipei, Taiwan

Shuen-Cheng Lei

This inventor holds 3 USPTO granted patents and 2 published patent applications. Top assignee: United Microelectronics Corp.. Active years: 2010-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shuen-Cheng Lei. Retrieved from https://idiyas.com/inventor/shuen-cheng-lei

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 3 

% Patents Active = 100.0

Average Co-Inventor Count = 5.6

ph-index = 2

Forward Citations = 5(Granted Patents)


Location History:

  • Tainan County, TW (2010)
  • Taipei County, TW (2013)

Company Filing History:


Years Active: 2010-2013

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3 patents (USPTO):Explore Patents

Title: Shuen-Cheng Lei: Innovator in Semiconductor Technology

Introduction

Shuen-Cheng Lei is a prominent inventor based in Taipei, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His innovative work focuses on methods that enhance the efficiency and reliability of semiconductor processes.

Latest Patents

One of his latest patents is titled "Method for predicting tolerable spacing between conductors in semiconductor process." This method provides a systematic approach to predicting tolerable contact-to-gate spacing. Initially, a wafer with multiple source/drain contacts is prepared. Subsequently, various testing gate lines are formed on the wafer using a photomask. In one die, different contact-to-gate distances are established, ranging from d+δd to d−δd, where d represents the standard spacing and δd is less than d. The wafer is then inspected to determine failure counts corresponding to each contact-to-gate distance. The tolerable spacing is calculated based on these failure counts and distances using a statistical method.

Another notable patent is "Method and pattern carrier for optimizing inspection recipe of defect inspection tool." This patent describes a method for optimizing the inspection recipe of a defect inspection tool. A substrate with intentional defects and locating patterns adjacent to these defects is utilized. The defect inspection tool detects the intentional defects using a specific inspection recipe, allowing for the identification of undetected or partially detected defects. The locating patterns help in determining the types of these undetected defects, leading to modifications in the inspection recipe to minimize undetected issues.

Career Highlights

Shuen-Cheng Lei is currently employed at United Microelectronics Corporation, a leading company in the semiconductor industry. His work at this organization has been instrumental in advancing semiconductor technologies and processes.

Collaborations

Throughout his career, Shuen-Cheng Lei has collaborated with notable colleagues, including Hsi-Hua Liu and Jen-Po Huang. These collaborations have contributed to the development of innovative solutions in semiconductor technology.

Conclusion

Shuen-Cheng Lei's contributions to semiconductor technology through his patents and work at United Microelectronics Corporation highlight his role as a key innovator in the field. His methods for optimizing semiconductor processes continue to influence advancements in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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