The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
Nov. 08, 2010
Chien-li Kuo, Hsinchu, TW;
Wen-jung Liao, Hsinchu, TW;
Jiun-hau Liao, Taipei County, TW;
Min-chin Hsieh, Hsinchu County, TW;
Chun-liang Hou, Hsinchu County, TW;
Shuen-cheng Lei, Taipei County, TW;
Chien-Li Kuo, Hsinchu, TW;
Wen-Jung Liao, Hsinchu, TW;
Jiun-Hau Liao, Taipei County, TW;
Min-Chin Hsieh, Hsinchu County, TW;
Chun-Liang Hou, Hsinchu County, TW;
Shuen-Cheng Lei, Taipei County, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+Δd to d−Δd wherein d is the standard spacing and Δd<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.