Shubhodeep Roy Choudhury

This inventor holds 10 USPTO granted patents. Top assignee: International Business Machines Corporation. Active years: 2009-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shubhodeep Roy Choudhury. Retrieved from https://idiyas.com/inventor/shubhodeep-roy-choudhury

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 10

% Patents Active = 50.0

Average Co-Inventor Count = 5.8

ph-index = 5

Forward Citations = 78(Granted Patents)

Company Filing History:

10 out of 166,351

International Business Machines Corporation

patents

Years Active: 2009-2012

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10 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8099559 - System and method for generating fast instruction and data interrupts for processor design verification and validation (2012-01-17),

2. 8019566 - System and method for efficiently testing cache congruence classes during processor design verification and validation (2011-09-13),

3. 8006221 - System and method for testing multiple processor modes for processor design verification and validation (2011-08-23),

4. 7992059 - System and method for testing a large memory area during processor design verification and validation (2011-08-02),

5. 7752499 - System and method for using resource pools and instruction pools for processor design verification and validation (2010-07-06),

6. 7747908 - System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation (2010-06-29),

7. 7739570 - System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation (2010-06-15),

8. 7669083 - System and method for re-shuffling test case instruction orders for processor design verification and validation (2010-02-23),

9. 7661023 - System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation (2010-02-09),

10. 7584394 - System and method for pseudo-random test pattern memory allocation for processor design verification and validation (2009-09-01),

Title: Innovations of Shubhodeep Roy Choudhury

Introduction

Shubhodeep Roy Choudhury is a prominent inventor based in Karnataka, India. He has made significant contributions to the field of processor design verification and validation. With a total of 10 patents to his name, his work has had a substantial impact on technology and innovation.

Latest Patents

One of his latest patents is a system and method for generating fast instruction and data interrupts for processor design verification and validation. This invention presents a method for intentionally invalidating translation entry valid bits to provoke storage interrupts during test case execution. The interrupt handler pseudo-randomly invalidates translation entries in a translation lookaside buffer (TLB) to trigger initial storage interrupts, such as instruction storage interrupts (ISI) or data storage interrupts (DSI). Another notable patent is a system and method for efficiently testing cache congruence classes during processor design verification and validation. This invention allows a single test case to test each sector within multiple congruence classes, enhancing the efficiency of the testing process.

Career Highlights

Shubhodeep Roy Choudhury is currently employed at International Business Machines Corporation (IBM). His work at IBM has allowed him to explore innovative solutions in processor design and validation. His contributions have been recognized within the industry, showcasing his expertise and commitment to advancing technology.

Collaborations

He has collaborated with notable coworkers such as Manoj Dusanapudi and Sunil Suresh Hatti. These collaborations have further enriched his work and contributed to the success of various projects.

Conclusion

Shubhodeep Roy Choudhury is a distinguished inventor whose work in processor design verification and validation has led to significant advancements in technology. His innovative patents and collaborations reflect his dedication to the field and his impact on the industry.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]