The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2009
Filed:
Jul. 18, 2007
Shubhodeep Roy Choudhury, Karnataka, IN;
Sandip Bag, Karnataka, IN;
Manoj Dusanapudi, Karnataka, IN;
Sunil Suresh Hatti, Karnataka, IN;
Shakti Kapoor, Austin, TX (US);
Bhavani Shringari Nanjundiah, Karnataka, IN;
Shubhodeep Roy Choudhury, Karnataka, IN;
Sandip Bag, Karnataka, IN;
Manoj Dusanapudi, Karnataka, IN;
Sunil Suresh Hatti, Karnataka, IN;
Shakti Kapoor, Austin, TX (US);
Bhavani Shringari Nanjundiah, Karnataka, IN;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes 'n' test patterns. In addition, the page table memory is allocated using a 'true' sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units.