System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation

Abstract

A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream 'holes' that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly.