Southborough, MA, United States of America

Shubhendu Sekhar Mukherjee

USPTO Granted Patents = 108 (Patent Applications = 9)

Average Co-Inventor Count = 2.1

ph-index = 12

Forward Citations = 571(Granted Patents)

Inventors with similar research interests:

Location History:

Framingham, MA (US) (2003 - 2012)
Southborough, MA (US) (2010 - 2024)
San Jose, CA (US) (2020 - 2024)

Company Filing History:

39 out of 1,123

Marvell Asia Pte., Ltd.

Hewlett-packard Development Company, L.p.

patents

5. 2 out of 1,901

Marvellworld Trade Ltd.

patents

Years Active: 2003-2025

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108 patents (USPTO):Sort by Forward Citations

Abstract keywords

1. 12293190 - Managing commit order for an external instruction relative to queued instructions (2025-05-06),

2. 12210457 - Processor data cache with shared mid-level cache and low-level cache (2025-01-28),

3. 12204904 - Dynamic designation of instructions as sensitive for constraining instruction execution (2025-01-21),

4. 12145518 - Managing power in an integrated circuit for high-speed activation (2024-11-19),

5. 11886882 - Pipelines for secure multithread execution (2024-01-30),

6. 11868262 - Methods and systems for distributing memory requests (2024-01-09),

7. 11842198 - Managing out-of-order retirement of instructions based on received instructions indicating start or stop to out-of-order retirement (2023-12-12),

8. 11822652 - Prime and probe attack mitigation (2023-11-21),

9. 11766975 - Managing power in an integrated circuit for high-speed activation (2023-09-26),

10. 11748109 - System and method for implementing strong load ordering in a processor using a circular ordering ring (2023-09-05),

11. 11615027 - Methods and systems for distributing memory requests (2023-03-28),

12. 11604873 - Noisy instructions for side-channel attack mitigation (2023-03-14),

13. 11550590 - System and method for implementing strong load ordering in a processor using a circular ordering ring (2023-01-10),

14. 11513958 - Shared mid-level data cache (2022-11-29),

15. 11507379 - Managing load and store instructions for memory barrier handling (2022-11-22),

As an AI assistant specialized in innovations, inventions, inventors, patent attorneys, assignees, and patents, I can provide you with the requested article about inventor Shubhendu Sekhar Mukherjee. Here is the structured information based on the data provided:

Title: Shubhendu Sekhar Mukherjee: Innovator in Secure Multithread Execution

Introduction:

Shubhendu Sekhar Mukherjee, a prolific innovator based in Southborough, MA (US), has made significant contributions in the field of secure multithread execution. With an impressive portfolio of 104 patents, Mukherjee continues to push the boundaries of technology and innovation.

Latest Patents:

Among his latest patents is "Pipelines for Secure Multithread Execution," which describes systems and methods for executing sensitive instructions in parallel threads securely. Additionally, Mukherjee has developed "Methods and Systems for Distributing Memory Requests," optimizing memory access for improved performance and efficiency.

Career Highlights:

Mukherjee has garnered extensive experience working with esteemed companies such as Marvell Asia Pte., Ltd. and Intel Corporation. His expertise in computer architecture and systems design has led to groundbreaking innovations in processor pipelines and memory management systems.

Collaborations:

Throughout his career, Mukherjee has collaborated with industry experts like Richard Eugene Kessler and David Albert Carlson. Together, they have pioneered advancements in semiconductor technology and memory hierarchy design, shaping the future of computing.

Conclusion:

In conclusion, Shubhendu Sekhar Mukherjee stands out as a trailblazer in the realm of secure multithread execution and memory optimization. His relentless pursuit of innovation and commitment to excellence continue to inspire the tech industry and pave the way for enhanced computational capabilities.

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9 patents pending:

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