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For the Inventor, By the Inventor

Southborough, MA, United States of America

Shubhendu Sekhar Mukherjee

This inventor holds 111 USPTO granted patents and 6 published patent applications, primarily in Integrated Circuit Design (CPC class G06F9-3836). Top assignees: Marvell Asia Pte., Ltd., Cavium, Inc., Intel Corporation. Active years: 2003-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shubhendu Sekhar Mukherjee. Retrieved from https://idiyas.com/inventor/shubhendu-sekhar-mukherjee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 111 

% Patents Active = 73.9

Average Co-Inventor Count = 2.1

ph-index = 13

Forward Citations = 604(Granted Patents)

Forward Citations (Not Self Cited) = 495(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Framingham, MA (US) (2003 - 2012)
  • Southborough, MA (US) (2010 - 2024)
  • San Jose, CA (US) (2020 - 2024)

Company Filing History:

goldMedal39 out of 1,237 
 
Marvell Asia Pte., Ltd.
 patents
silverMedal30 out of 448 
 
Cavium, Inc.
 patents
bronzeMedal30 out of 56,365 
 
Intel Corporation
 patents
4. 7 out of 27,687 
 
Hewlett-Packard Development Company, L.p.
 patents
5. 3 out of 112 
 
Sifive, Inc.
 patents
6. 2 out of 1,901 
 
Marvellworld Trade Ltd.
 patents

Years Active: 2003-2026

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Areas of Expertise:
Error Management
Processor Cache
Power Management
Instruction Execution
Multithread Execution
Memory Requests
Side-Channel Attack
Cache Misses
Load Ordering
Prefetching
Core Synchronization
Translation Lookaside Buffer
111 patents (USPTO):Explore Patents
1. 12711076 - PAGE TABLE ENTRY CACHES WITH MULTIPLE TAG LENGTHS (2026-08-18),
2. 12710984 - Processor Power Management Using Instruction Throttling (2026-08-18),
3. 12517841 - Error management in system on a chip with securely partitioned memory space (2026-01-06),
4. 12293190 - Managing commit order for an external instruction relative to queued instructions (2025-05-06),
5. 12210457 - Processor data cache with shared mid-level cache and low-level cache (2025-01-28),
6. 12204904 - Dynamic designation of instructions as sensitive for constraining instruction execution (2025-01-21),
7. 12145518 - Managing power in an integrated circuit for high-speed activation (2024-11-19),
8. 11886882 - Pipelines for secure multithread execution (2024-01-30),
9. 11868262 - Methods and systems for distributing memory requests (2024-01-09),
10. 11842198 - Managing out-of-order retirement of instructions based on received instructions indicating start or stop to out-of-order retirement (2023-12-12),
11. 11822652 - Prime and probe attack mitigation (2023-11-21),
12. 11766975 - Managing power in an integrated circuit for high-speed activation (2023-09-26),
13. 11748109 - System and method for implementing strong load ordering in a processor using a circular ordering ring (2023-09-05),
14. 11615027 - Methods and systems for distributing memory requests (2023-03-28),
15. 11604873 - Noisy instructions for side-channel attack mitigation (2023-03-14),

As an AI assistant specialized in innovations, inventions, inventors, patent attorneys, assignees, and patents, I can provide you with the requested article about inventor Shubhendu Sekhar Mukherjee. Here is the structured information based on the data provided:

Title: Shubhendu Sekhar Mukherjee: Innovator in Secure Multithread Execution

Introduction:

Shubhendu Sekhar Mukherjee, a prolific innovator based in Southborough, MA (US), has made significant contributions in the field of secure multithread execution. With an impressive portfolio of 104 patents, Mukherjee continues to push the boundaries of technology and innovation.

Latest Patents:

Among his latest patents is "Pipelines for Secure Multithread Execution," which describes systems and methods for executing sensitive instructions in parallel threads securely. Additionally, Mukherjee has developed "Methods and Systems for Distributing Memory Requests," optimizing memory access for improved performance and efficiency.

Career Highlights:

Mukherjee has garnered extensive experience working with esteemed companies such as Marvell Asia Pte., Ltd. and Intel Corporation. His expertise in computer architecture and systems design has led to groundbreaking innovations in processor pipelines and memory management systems.

Collaborations:

Throughout his career, Mukherjee has collaborated with industry experts like Richard Eugene Kessler and David Albert Carlson. Together, they have pioneered advancements in semiconductor technology and memory hierarchy design, shaping the future of computing.

Conclusion:

In conclusion, Shubhendu Sekhar Mukherjee stands out as a trailblazer in the realm of secure multithread execution and memory optimization. His relentless pursuit of innovation and commitment to excellence continue to inspire the tech industry and pave the way for enhanced computational capabilities.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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