The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Sep. 29, 2020
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventors:

Shubhendu Sekhar Mukherjee, Southborough, MA (US);

David Albert Carlson, Haslet, TX (US);

Michael Bertone, Marlborough, MA (US);

Assignee:

Marvell Asia Pte, Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2017.12); G06F 9/30 (2017.12);
U.S. Cl.
CPC ...
G06F 9/3836 (2012.12); G06F 9/30076 (2012.12); G06F 9/30087 (2012.12); G06F 9/3854 (2023.07); G06F 2212/683 (2012.12);
Abstract

In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.


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