The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Nov. 18, 2021
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventors:

Richard E. Kessler, San Jose, CA (US);

David Asher, San Jose, CA (US);

Shubhendu S. Mukherjee, San Jose, CA (US);

Wilson P. Snyder, II, San Jose, CA (US);

David Carlson, San Jose, CA (US);

Jason Zebchuk, San Jose, CA (US);

Isam Akkawi, San Jose, CA (US);

Assignee:

Marvell Asia Pte, Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0844 (2016.01); G06F 12/0813 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0844 (2013.01); G06F 12/0813 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/608 (2013.01);
Abstract

A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.


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