Shalini Pathak

Title: Shalini Pathak: Innovator in Scan Test Systems

Introduction

Shalini Pathak is a prominent inventor based in Haryana, India. She has made significant contributions to the field of scan test systems, holding a total of 7 patents. Her innovative work focuses on improving testing methodologies for integrated circuits.

Latest Patents

One of her latest patents is titled "Partial Chain Reconfiguration for Test Time Reduction." This invention involves a method for testing a scan chain by segmenting it into multiple segments and utilizing multiplexers to rearrange their positions. The method generates test patterns and observes results to determine fault conditions effectively. Another notable patent is the "Compression-Based Scan Test System," which describes a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system. This system generates test patterns, modifies bit distributions, and captures response patterns from circuits under test.

Career Highlights

Shalini has worked with reputable companies such as STMicroelectronics International N.V. and STMicroelectronics Pvt. Ltd. Her experience in these organizations has allowed her to refine her skills and contribute to cutting-edge technologies in the semiconductor industry.

Collaborations

Throughout her career, Shalini has collaborated with talented professionals, including Sandeep Jain and Parvesh Swami. These collaborations have fostered innovation and enhanced the development of her patented technologies.

Conclusion

Shalini Pathak is a remarkable inventor whose work in scan test systems has paved the way for advancements in integrated circuit testing. Her contributions are invaluable to the field, and her patents reflect her dedication to innovation.