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For the Inventor, By the Inventor

Tokyo, Japan

Seiji Yamada

This inventor holds 19 USPTO granted patents and 2 published patent applications and 1 EPO patent, primarily in Semiconductor Memory. Top assignees: Kabushiki Kaisha Toshiba, Bridgestone Corporation, Akihisa Inoue. Active years: 1991-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Seiji Yamada. Retrieved from https://idiyas.com/inventor/seiji-yamada-dfx4op06

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 19 

% Patents Active = 100.0

 

Average Co-Inventor Count = 2.1

ph-index = 8

Forward Citations = 229(Granted Patents)


Location History:

  • Kodaira, JP (2000)
  • Shinagawa-Ku, JP (2004)
  • Tokyo, JP (1991 - 2015)

Company Filing History:

goldMedal15 out of 53,276 
 
Kabushiki Kaisha Toshiba
 patents
silverMedal3 out of 5,195 
 
Bridgestone Corporation
 patents
bronzeMedal1 out of 2 
 
Akihisa Inoue
 patents
4. 1 out of 1,052 
 
Tohoku University
 patents
5. 1 out of 91 
 
Topy Kogyo Kabushiki Kaisha
 patents
where one patent can have more than one assignee

Years Active: 1991-2015

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Areas of Expertise:
Nonvolatile Memory
Semiconductor Device
Memory Manufacturing
Data Erasing
Memory Cell
Programming Method
Flash Memory
Memory Layout
Automobile Tire
Metallic Glass Laminates
Pneumatic Tires
Channel Structure
19 patents (USPTO):Explore Patents
1. D726102 - Tread portion of an automobile tire (2015-04-07),
2. D675559 - Tread portion of an automobile tire (2013-02-05),
3. 7906219 - Metallic glass laminates, production methods and applications thereof (2011-03-15),
4. 6828622 - Nonvolatile semiconductor memory device and its manufacturing method (2004-12-07),
5. 6441427 - NOR-type flash memory and method for manufacturing the same (2002-08-27),
6. 6256227 - Non-volatile semiconductor memory having column sub-selector layout pattern adaptable to miniaturization of memory cell (2001-07-03),
7. 6222773 - Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing (2001-04-24),
8. 6145560 - Heavy duty pneumatic radial tires with specified belt cushion rubbers (2000-11-14),
9. 6118697 - Nonvolatile semiconductor memory in which the number of programming or (2000-09-12),
10. 5754558 - Method and apparatus for screening a nonvolatile semiconductor memory (1998-05-19),
11. 5751636 - Semiconductor memory device having data erasing mechanism (1998-05-12),
12. 5623445 - Semiconductor memory device having data erasing mechanism (1997-04-22),
13. 5586073 - Semiconductor device having a multi-layer channel structure (1996-12-17),
14. 5452248 - Method of operating a nonvolatile semiconductor memory device (1995-09-19),
15. 5432109 - Device method for manufacturing a semiconductor memory (1995-07-11),

Title: Seiji Yamada: Pioneering Inventor from Tokyo

Introduction: Seiji Yamada is a renowned inventor hailing from Tokyo, Japan, known for his groundbreaking contributions to various technological fields.

Latest Patents: Seiji Yamada holds several patents in the areas of robotics, artificial intelligence, and renewable energy technologies, showcasing his innovative spirit and forward-thinking approach.

Career Highlights: With over two decades of experience in the tech industry, Seiji Yamada has worked with leading research institutions and multinational corporations, spearheading projects that have revolutionized the way we interact with technology on a daily basis.

Collaborations: Throughout his career, Seiji Yamada has collaborated with top engineers, scientists, and designers from around the world, fostering a culture of creativity and excellence in all his projects.

Conclusion: Seiji Yamada's relentless pursuit of innovation and his passion for pushing the boundaries of what is possible make him a true visionary in the world of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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