Non-volatile semiconductor memory having column sub-selector layout pattern adaptable to miniaturization of memory cell

Abstract

A pattern constituted of a main bit line and four sub-bit lines is repeated around a column sub-selector of the flash EEPROM employing a double bit architecture having four block selection transistors per pitch of the pattern. In the flash EEPROM having a memory cell array and a column selector divided into a plurality of cell blocks,and a plurality of column sub selectors,, respectively, the column sub-selector including repeated patterns each having four sub bit lines (SBLs) and a single main bit line (MBL) arranged in a column direction. In a pitch of the repeating pattern, active regions for four block selection transistors (BSTs) are arranged. Gate wiring layers of each of the block selection transistors are arranged above the active region in a row direction and four block decode lines (BDL,) are arranged above the active region in the row direction.