The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2004

Filed:

Sep. 09, 1999
Applicant:
Inventors:

Shota Kitamura, Kawasaki, JP;

Seiji Yamada, Shinagawa-Ku, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/9788 ;
U.S. Cl.
CPC ...
H01L 2/9788 ;
Abstract

Memory cells each having a floating gate ( ), control gate ( ), and source and drain diffusion layers ( ) are formed on a silicon substrate ( ). A silicon nitride film ( ) by low-pressure CVD is maintained as side wall insulating films on side walls of the gates in each memory cell. A silicon nitride film ( ) by plasma CVD is formed to cover a memory cell array, and silicon oxide films ( ) are made on the silicon nitride film ( ) to form an inter-layer insulating film. A common source line ( ) connected to the source diffusion layer is formed to embed in the silicon oxide film ( ), and a bit line ( ) connected to the drain diffusion layer ( ) is formed on the silicon oxide film ( ).


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