Lompoc, CA, United States of America

Sean P Kilcoyne

This inventor holds 26 USPTO granted patents and 5 published patent applications, plus 1 CIPO patent and 7 EPO patents, primarily in Semiconductor Technology. Top assignees: Raytheon Company, Gore Enterprise Holdings, Inc.. Active years: 2000-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sean P Kilcoyne. Retrieved from https://idiyas.com/inventor/sean-p-kilcoyne

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 26 

% Patents Active = 96.2

 

 

Average Co-Inventor Count = 3.6

ph-index = 2

Forward Citations = 40(Granted Patents)


Location History:

  • Waltham, MA (US) (2019 - 2022)
  • Lompoc, CA (US) (2000 - 2024)

Company Filing History:


Years Active: 2000-2026

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Areas of Expertise:
Dielectric Layer
3D Integration
Imaging Arrays
Wafer Bonding
Photonic Devices
Optical Detectors
Interconnects
Calibration Structures
Thin Film
Signal Pathways
Electrical Devices
Variable Technology
26 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Sean P Kilcoyne

Introduction: Sean P Kilcoyne, an accomplished inventor based in Lompoc, CA, has made significant strides in the fields of semiconductor technology and interconnect fabrication. With a portfolio of 22 patents, Kilcoyne's innovative ideas have furthered advancements within the industry.

Latest Patents: Among Sean’s latest inventions are two notable patents. The first, titled "Iterative formation of damascene interconnects - Interconnects and methods of fabricating a plurality of interconnects," encompasses a method that includes depositing a conformal layer of a plating base in multiple vias, accompanied by the deposition of a photoresist. The process ensures that the plating metal fills each via completely or incompletely, followed by a thorough chemical mechanical planarization (CMP). This method employs iterative processes if any vias remain incompletely filled.

The second patent, "Close butted collocated variable technology imaging arrays on a single ROIC," introduces a semiconductor-based imaging device. This patent details a method of forming a direct bond hybridization (DBH) structure on a readout integrated circuit (ROIC) and bonds silicon and non-silicon-based detectors to the ROIC, enhancing imaging capabilities.

Career Highlights: Sean P Kilcoyne has built an impressive career by gaining experience with leading companies in the technology sector. He has notably contributed to Raytheon Company and Gore Enterprise Holdings, Inc., where he has harnessed his skills in innovation and technology development.

Collaborations: Throughout his career, Sean has collaborated with esteemed professionals, including Eric R Miller and John L Vampola. These partnerships have played a vital role in driving innovation and enhancing the quality of his inventions, strengthening the industry landscape.

Conclusion: Sean P Kilcoyne's commitment to innovation is evident through his extensive patent portfolio and professional collaborations. With continual advancements in semiconductor technology and interconnect fabrication, his contributions serve as a testament to his ingenuity and dedication to the field. As technology continues to evolve, the impact of Kilcoyne's work will undoubtedly resonate across the industry for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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