Raytheon Company

Gore Enterprise Holdings, Inc.

Sean P Kilcoyne

Eric R Miller

John L Vampola

George Grama

Justin Gordon Adams Wehner

Michael V Liguori

Scott S Miller

Theodore D Lowes

Adam M Kennedy

Christian M Boemler

Michael J Rondon

Mark Nathaniel Donhowe

Robert F Traver, Jr

Drew Fairbanks

Eric Miller

Jeffery H Burkhart

John J Drab

Micky R Harris

Kenton T Veeder

Michael Kennedy Burkland

Eric J Beuville

David J Gulbransen

Jamal I Mustafa

William H Frye

Michael J Batinica

Matthew D Chambers

George Paloczi

Chad W Fulk

Robert C Anderson

Thomas R Yengst

Andrew Cahill

Christopher Lynn Mears

Neil R Malone

Scott M Taylor

Richard E Wahl

Paul Bryant

Shannon F Wilkey

Peter A Bellus

Andrew E Gin

Robert M Emerson

Christine Frandsen

Barry M Starr

Christopher Casimir Brough

Robert E Mills

Christopher L Mears

Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.

Integrated circuit having vertical routing to bond pads

Methods and apparatus for an assembly having a first wafer including bulk material and a layer having microelectronics and a wafer with a deposited thin film which is bonded to the first wafer such that the reflected film is embedded within the composed assembly. The reflector wafer can include a handle wafer and a thin film having reflectance characteristics to prevent imaging of the microelectronics via light through the bulk material.

Thin film obscurant for microelectronics

A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.

Mosaic focal plane array

Interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

Iterative formation of damascene interconnects

A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

Close butted collocated variable technology imaging arrays on a single ROIC

A scalable independent unit cell device architecture may include a phase-shifting element and a phase shift driver both integrated within the unit cell device. The phase shift driver may be coupled to the phase-shifting element and the phase shift driver may independently control the phase-shifting element to produce an optical beam having a desired phase. The unit cell device may further include an optical antenna that outputs the beam having the desired phase. The unit cell device may be formed as an opto-electronic hybrid optimized to leverage direct bond hybridization (DBH) to attach an electronic integrated circuit wafer to a side of a photonic integrated circuit wafer. The resulting unit cell device (i.e., 24 microns) may tightly integrate individual element-level phase control, which may be implemented within large-scale two-dimensional photonic arrays with hemispherical beam steering.

Scalable unit cell device for large two-dimensional arrays with integrated phase control

An imaging and asynchronous laser pulse detector (ALPD) device, imaging cell of the imaging and ALPD device and method of use is disclosed. A detector generates an electrical signal in response to receiving an optical signal, wherein a frequency of the electrical signal is indicative of a frequency of the optical signal. A first detection/readout circuit is sensitive to a first frequency range, and a second detection/readout circuit is sensitive to a second frequency range. The first detection/readout circuit allows the electrical signal to pass from the first detection/readout circuit to the second detection/readout circuit.

Imager with integrated asynchronous laser pulse detection having a signal component along a second electrical pathway passes through an ALPD readout integrated circuit to an imaging readout integrated circuit

A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

Integrating optical elements with electro-optical sensors via direct-bond hybridization

Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

An integrated circuit assembly including a first wafer bonded to a second wafer with an oxide layer, wherein a first surface of the first wafer is bonded to a first surface of the second wafer. The assembly can include a bonding oxide on a second surface of the second wafer, wherein a surface of the bonding oxide is polished. The assembly can further include a shim secured to the bonding oxide on the second surface of the second wafer to reduce bow of the circuit assembly.

Wafer level shim processing

A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.

Method of manufacturing wafer level low melting temperature interconnections

A three-dimensional (3D) stack is provided and includes a capacitor layer and an integrated circuit (IC) layer. The capacitor layer includes capacitors and capacitor layer connectors respectively communicative with corresponding capacitors. The IC layer is stacked vertically with the capacitor layer and is hybridized to a detector. The IC layer includes IC layer connectors respectively communicative with corresponding capacitor layer connectors.

Stacked sensor with integrated capacitors

Disclosed is a process for manufacturing individual die devices, with a desired or predicted amount of flatness, from a bonded wafer process. The flatness of a bonded wafer is measured at point in the wafer manufacturing process. This measurement is compared to a value predetermined by an empirical analysis of previous devices made by the same process. If the flatness of the bonded wafer is not at the predetermined value, then one or more compensation layers are provided to the bonded wafer to obtain the predetermined flatness value. Once obtained, subsequent processing is performed and the resulting individual dies are obtained with the desired flatness characteristic.

Stress compensation and relief in bonded wafers

Growing community of inventors

Lompoc, CA, United States of America

Sean P Kilcoyne